Kconfig 4.28 KB
Newer Older
1
config ARCH_LS1012A
2
	bool
3
	select FSL_LSCH2
4
	select SYS_FSL_DDR_BE
5
	select SYS_FSL_MMDC
6
7
8
	select SYS_FSL_ERRATUM_A010315

config ARCH_LS1043A
9
	bool
10
	select FSL_LSCH2
11
	select SYS_FSL_DDR
12
13
	select SYS_FSL_DDR_BE
	select SYS_FSL_DDR_VER_50
14
15
16
17
18
	select SYS_FSL_ERRATUM_A008850
	select SYS_FSL_ERRATUM_A009660
	select SYS_FSL_ERRATUM_A009663
	select SYS_FSL_ERRATUM_A009929
	select SYS_FSL_ERRATUM_A009942
19
	select SYS_FSL_ERRATUM_A010315
20
	select SYS_FSL_ERRATUM_A010539
21
22
	select SYS_FSL_HAS_DDR3
	select SYS_FSL_HAS_DDR4
23

24
config ARCH_LS1046A
25
	bool
26
	select FSL_LSCH2
27
	select SYS_FSL_DDR
28
29
	select SYS_FSL_DDR_BE
	select SYS_FSL_DDR_VER_50
30
31
32
33
34
	select SYS_FSL_ERRATUM_A008511
	select SYS_FSL_ERRATUM_A009801
	select SYS_FSL_ERRATUM_A009803
	select SYS_FSL_ERRATUM_A009942
	select SYS_FSL_ERRATUM_A010165
35
	select SYS_FSL_ERRATUM_A010539
36
	select SYS_FSL_HAS_DDR4
37
	select SYS_FSL_SRDS_2
38

39
40
config ARCH_LS2080A
	bool
41
	select FSL_LSCH3
42
	select SYS_FSL_DDR
43
44
	select SYS_FSL_DDR_LE
	select SYS_FSL_DDR_VER_50
45
	select SYS_FSL_HAS_DP_DDR
46
	select SYS_FSL_HAS_SEC
47
	select SYS_FSL_HAS_DDR4
48
	select SYS_FSL_SEC_COMPAT_5
49
	select SYS_FSL_SEC_LE
50
	select SYS_FSL_SRDS_2
51
52
53
54
55
56
57
58
59
60
	select SYS_FSL_ERRATUM_A008336
	select SYS_FSL_ERRATUM_A008511
	select SYS_FSL_ERRATUM_A008514
	select SYS_FSL_ERRATUM_A008585
	select SYS_FSL_ERRATUM_A009635
	select SYS_FSL_ERRATUM_A009663
	select SYS_FSL_ERRATUM_A009801
	select SYS_FSL_ERRATUM_A009803
	select SYS_FSL_ERRATUM_A009942
	select SYS_FSL_ERRATUM_A010165
61
62
63

config FSL_LSCH2
	bool
64
65
	select SYS_FSL_HAS_SEC
	select SYS_FSL_SEC_COMPAT_5
66
	select SYS_FSL_SEC_BE
67
68
	select SYS_FSL_SRDS_1
	select SYS_HAS_SERDES
69
70
71

config FSL_LSCH3
	bool
72
73
	select SYS_FSL_SRDS_1
	select SYS_HAS_SERDES
74
75
76

menu "Layerscape architecture"
	depends on FSL_LSCH2 || FSL_LSCH3
77

78
79
80
81
82
83
84
85
86
87
88
config FSL_PCIE_COMPAT
	string "PCIe compatible of Kernel DT"
	depends on PCIE_LAYERSCAPE
	default "fsl,ls1012a-pcie" if ARCH_LS1012A
	default "fsl,ls1043a-pcie" if ARCH_LS1043A
	default "fsl,ls1046a-pcie" if ARCH_LS1046A
	default "fsl,ls2080a-pcie" if ARCH_LS2080A
	help
	  This compatible is used to find pci controller node in Kernel DT
	  to complete fixup.

89
90
91
menu "Layerscape PPA"
config FSL_LS_PPA
	bool "FSL Layerscape PPA firmware support"
92
	depends on !ARMV8_PSCI
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
	depends on ARCH_LS1043A || ARCH_LS1046A
	select FSL_PPA_ARMV8_PSCI
	help
	  The FSL Primary Protected Application (PPA) is a software component
	  which is loaded during boot stage, and then remains resident in RAM
	  and runs in the TrustZone after boot.
	  Say y to enable it.

config FSL_PPA_ARMV8_PSCI
	bool "PSCI implementation in PPA firmware"
	depends on FSL_LS_PPA
	help
	  This config enables the ARMv8 PSCI implementation in PPA firmware.
	  This is a private PSCI implementation and different from those
	  implemented under the common ARMv8 PSCI framework.
endmenu

110
111
config SYS_FSL_ERRATUM_A010315
	bool "Workaround for PCIe erratum A010315"
112
113
114

config SYS_FSL_ERRATUM_A010539
	bool "Workaround for PIN MUX erratum A010539"
115

York Sun's avatar
York Sun committed
116
117
118
119
120
121
122
123
124
125
126
127
128
config MAX_CPUS
	int "Maximum number of CPUs permitted for Layerscape"
	default 4 if ARCH_LS1043A
	default 4 if ARCH_LS1046A
	default 16 if ARCH_LS2080A
	default 1
	help
	  Set this number to the maximum number of possible CPUs in the SoC.
	  SoCs may have multiple clusters with each cluster may have multiple
	  ports. If some ports are reserved but higher ports are used for
	  cores, count the reserved ports. This will allocate enough memory
	  in spin table to properly handle all cores.

129
130
131
132
133
config SECURE_BOOT
	bool
	help
		Enable Freescale Secure Boot feature

134
135
136
137
138
139
140
config QSPI_AHB_INIT
	bool "Init the QSPI AHB bus"
	help
	  The default setting for QSPI AHB bus just support 3bytes addressing.
	  But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
	  bus for those flashes to support the full QSPI flash size.

141
142
143
144
145
146
147
config SYS_FSL_IFC_BANK_COUNT
	int "Maximum banks of Integrated flash controller"
	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
	default 4 if ARCH_LS1043A
	default 4 if ARCH_LS1046A
	default 8 if ARCH_LS2080A

148
149
150
config SYS_FSL_HAS_DP_DDR
	bool

151
152
153
154
155
156
157
158
159
config SYS_FSL_SRDS_1
	bool

config SYS_FSL_SRDS_2
	bool

config SYS_HAS_SERDES
	bool

160
endmenu
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181

config SYS_FSL_ERRATUM_A008336
	bool

config SYS_FSL_ERRATUM_A008514
	bool

config SYS_FSL_ERRATUM_A008585
	bool

config SYS_FSL_ERRATUM_A008850
	bool

config SYS_FSL_ERRATUM_A009635
	bool

config SYS_FSL_ERRATUM_A009660
	bool

config SYS_FSL_ERRATUM_A009929
	bool