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Commit 8a316c9b authored by Stefan Roese's avatar Stefan Roese Committed by Stefan Roese
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Major cleanup for AMCC PPC4xx eval boards. 

Patch by Stefan Roese, 01 Aug 2005
parent c157d8e2
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CHANGELOG
View file @ 8a316c9b
...@@ -2,6 +2,18 @@ ...@@ -2,6 +2,18 @@
Changes for U-Boot 1.1.3: Changes for U-Boot 1.1.3:
====================================================================== ======================================================================
* Patch by Stefan Roese, 01 Aug 2005:
- Major cleanup for AMCC eval boards Walnut, Bubinga, Ebony, Ocotea
(former IBM eval board). Please see "doc/README.AMCC-eval-boards-cleanup"
for details.
- Sycamore (PPC405GPr) eval board added (Walnut port is extended
to run on both 405GP and 405GPr eval boards).
* Patch by Steven Blakeslee, 27 Jul 2005:
- Add support for AMCC PPC440EP/GR.
- Add support for AMCC Yosemite PPC440EP eval board.
- Add support for AMCC Yellowstone PPC440GR eval board.
* Fix sysmon POST problem: check I2C error codes * Fix sysmon POST problem: check I2C error codes
This fixes a problem of displaying bogus voltages when the voltages This fixes a problem of displaying bogus voltages when the voltages
are so low that the I2C devices start failing while the rest of the are so low that the I2C devices start failing while the rest of the
......
MAINTAINERS
View file @ 8a316c9b
...@@ -210,6 +210,11 @@ Keith Outwater <Keith_Outwater@mvis.com> ...@@ -210,6 +210,11 @@ Keith Outwater <Keith_Outwater@mvis.com>
GEN860T MPC860T GEN860T MPC860T
GEN860T_SC MPC860T GEN860T_SC MPC860T
Stefan Roese <sr@denx.de>
sycamore PPC4xx
walnut PPC4xx
Frank Panno <fpanno@delphintech.com> Frank Panno <fpanno@delphintech.com>
ep8260 MPC8260 ep8260 MPC8260
...@@ -327,7 +332,6 @@ Unknown / orphaned boards: ...@@ -327,7 +332,6 @@ Unknown / orphaned boards:
CRAYL1 PPC4xx CRAYL1 PPC4xx
ERIC PPC4xx ERIC PPC4xx
WALNUT405 PPC4xx
MOUSSE MPC824x MOUSSE MPC824x
......
MAKEALL
View file @ 8a316c9b
...@@ -60,16 +60,17 @@ LIST_8xx=" \ ...@@ -60,16 +60,17 @@ LIST_8xx=" \
######################################################################### #########################################################################
LIST_4xx=" \ LIST_4xx=" \
ADCIOP AR405 ASH405 BUBINGA405EP \ ADCIOP AR405 ASH405 bubinga \
CANBT CPCI405 CPCI4052 CPCI405AB \ CANBT CPCI405 CPCI4052 CPCI405AB \
CPCI440 CPCIISER4 CRAYL1 csb272 \ CPCI440 CPCIISER4 CRAYL1 csb272 \
csb472 DASA_SIM DP405 DU405 \ csb472 DASA_SIM DP405 DU405 \
EBONY ERIC EXBITGEN HUB405 \ ebony ERIC EXBITGEN HUB405 \
JSE MIP405 MIP405T ML2 \ JSE MIP405 MIP405T ML2 \
ml300 OCOTEA OCRTC ORSG \ ml300 ocotea OCRTC ORSG \
PCI405 PIP405 PLU405 PMC405 \ PCI405 PIP405 PLU405 PMC405 \
PPChameleonEVB VOH405 W7OLMC W7OLMG \ PPChameleonEVB VOH405 W7OLMC W7OLMG \
WALNUT405 WUH405 XPEDITE1K \ walnut WUH405 XPEDITE1K yellowstone \
yosemite \
" "
######################################################################### #########################################################################
......
Makefile
View file @ 8a316c9b
...@@ -707,8 +707,11 @@ AR405_config: unconfig ...@@ -707,8 +707,11 @@ AR405_config: unconfig
ASH405_config: unconfig ASH405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ash405 esd @./mkconfig $(@:_config=) ppc ppc4xx ash405 esd
BUBINGA405EP_config: unconfig bamboo_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx bubinga405ep @./mkconfig $(@:_config=) ppc ppc4xx bamboo amcc
bubinga_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx bubinga amcc
CANBT_config: unconfig CANBT_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx canbt esd @./mkconfig $(@:_config=) ppc ppc4xx canbt esd
...@@ -759,8 +762,8 @@ DP405_config: unconfig ...@@ -759,8 +762,8 @@ DP405_config: unconfig
DU405_config: unconfig DU405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx du405 esd @./mkconfig $(@:_config=) ppc ppc4xx du405 esd
EBONY_config: unconfig ebony_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ebony @./mkconfig $(@:_config=) ppc ppc4xx ebony amcc
ERIC_config: unconfig ERIC_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx eric @./mkconfig $(@:_config=) ppc ppc4xx eric
...@@ -794,8 +797,8 @@ ML2_config: unconfig ...@@ -794,8 +797,8 @@ ML2_config: unconfig
ml300_config: unconfig ml300_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx @./mkconfig $(@:_config=) ppc ppc4xx ml300 xilinx
OCOTEA_config: unconfig ocotea_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx ocotea @./mkconfig $(@:_config=) ppc ppc4xx ocotea amcc
OCRTC_config \ OCRTC_config \
ORSG_config: unconfig ORSG_config: unconfig
...@@ -846,6 +849,10 @@ PPChameleonEVB_HI_33_config: unconfig ...@@ -846,6 +849,10 @@ PPChameleonEVB_HI_33_config: unconfig
sbc405_config: unconfig sbc405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx sbc405 @./mkconfig $(@:_config=) ppc ppc4xx sbc405
sycamore_config: unconfig
@echo "Configuring for sycamore board as subset of walnut..."
@./mkconfig -a walnut ppc ppc4xx walnut amcc
VOH405_config: unconfig VOH405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx voh405 esd @./mkconfig $(@:_config=) ppc ppc4xx voh405 esd
...@@ -856,8 +863,8 @@ W7OLMC_config \ ...@@ -856,8 +863,8 @@ W7OLMC_config \
W7OLMG_config: unconfig W7OLMG_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx w7o @./mkconfig $(@:_config=) ppc ppc4xx w7o
WALNUT405_config: unconfig walnut_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx walnut405 @./mkconfig $(@:_config=) ppc ppc4xx walnut amcc
WUH405_config: unconfig WUH405_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx wuh405 esd @./mkconfig $(@:_config=) ppc ppc4xx wuh405 esd
...@@ -865,6 +872,12 @@ WUH405_config: unconfig ...@@ -865,6 +872,12 @@ WUH405_config: unconfig
XPEDITE1K_config: unconfig XPEDITE1K_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx xpedite1k @./mkconfig $(@:_config=) ppc ppc4xx xpedite1k
yosemite_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx yosemite amcc
yellowstone_config: unconfig
@./mkconfig $(@:_config=) ppc ppc4xx yellowstone amcc
######################################################################### #########################################################################
## MPC8220 Systems ## MPC8220 Systems
######################################################################### #########################################################################
......
README
View file @ 8a316c9b
...@@ -295,7 +295,7 @@ The following options need to be configured: ...@@ -295,7 +295,7 @@ The following options need to be configured:
CONFIG_FADS823 CONFIG_NETVIA CONFIG_V37 CONFIG_FADS823 CONFIG_NETVIA CONFIG_V37
CONFIG_FADS850SAR CONFIG_NX823 CONFIG_W7OLMC CONFIG_FADS850SAR CONFIG_NX823 CONFIG_W7OLMC
CONFIG_FADS860T CONFIG_OCRTC CONFIG_W7OLMG CONFIG_FADS860T CONFIG_OCRTC CONFIG_W7OLMG
CONFIG_FLAGADM CONFIG_ORSG CONFIG_WALNUT405 CONFIG_FLAGADM CONFIG_ORSG CONFIG_WALNUT
CONFIG_FPS850L CONFIG_OXC CONFIG_ZPC1900 CONFIG_FPS850L CONFIG_OXC CONFIG_ZPC1900
CONFIG_FPS860L CONFIG_ZUMA CONFIG_FPS860L CONFIG_ZUMA
...@@ -2192,7 +2192,7 @@ configurations; the following names are supported: ...@@ -2192,7 +2192,7 @@ configurations; the following names are supported:
FADS850SAR_config omap1610h2_config TQM850L_config FADS850SAR_config omap1610h2_config TQM850L_config
FADS860T_config omap1610inn_config TQM855L_config FADS860T_config omap1610inn_config TQM855L_config
FPS850L_config omap5912osk_config TQM860L_config FPS850L_config omap5912osk_config TQM860L_config
omap2420h4_config WALNUT405_config omap2420h4_config walnut_config
Yukon8220_config Yukon8220_config
ZPC1900_config ZPC1900_config
...@@ -3135,7 +3135,7 @@ locked as (mis-) used as memory, etc. ...@@ -3135,7 +3135,7 @@ locked as (mis-) used as memory, etc.
CFG_INIT_RAM_ADDR should be somewhere that won't interfere CFG_INIT_RAM_ADDR should be somewhere that won't interfere
with your processor/board/system design. The default value with your processor/board/system design. The default value
you will find in any recent u-boot distribution in you will find in any recent u-boot distribution in
Walnut405.h should work for you. I'd set it to a value larger walnut.h should work for you. I'd set it to a value larger
than your SDRAM module. If you have a 64MB SDRAM module, set than your SDRAM module. If you have a 64MB SDRAM module, set
it above 400_0000. Just make sure your board has no resources it above 400_0000. Just make sure your board has no resources
that are supposed to respond to that address! That code in that are supposed to respond to that address! That code in
......
board/amcc/bamboo/Makefile 0 → 100644
View file @ 8a316c9b
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o
#OBJS += flash.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################
board/amcc/bamboo/bamboo.c 0 → 100644
View file @ 8a316c9b
/*
* (C) Copyright 2005
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>
int board_early_init_f(void)
{
register uint reg;
/*--------------------------------------------------------------------
* Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/
mtdcr(ebccfga, xbcfg);
reg = mfdcr(ebccfgd);
mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
#if 0 /* test-only */
mtebc(pb0ap, 0x03017300); /* FLASH/SRAM */
mtebc(pb0cr, 0xfe0ba000); /* BAS=0xfe0 32MB r/w 16-bit */
mtebc(pb1ap, 0x00000000);
mtebc(pb1cr, 0x00000000);
mtebc(pb2ap, 0x04814500);
/*CPLD*/ mtebc(pb2cr, 0x80018000); /*BAS=0x800 1MB r/w 8-bit */
#else
mtebc(pb0ap, 0x04055200); /* FLASH/SRAM */
mtebc(pb0cr, 0xfff18000); /* BAS=0xfe0 1MB r/w 8-bit */
#endif
mtebc(pb3ap, 0x00000000);
mtebc(pb3cr, 0x00000000);
mtebc(pb4ap, 0x00000000);
mtebc(pb4cr, 0x00000000);
mtebc(pb5ap, 0x00000000);
mtebc(pb5cr, 0x00000000);
/*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000009); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
/*--------------------------------------------------------------------
* Setup the GPIO pins
*-------------------------------------------------------------------*/
/*CPLD cs */
/*setup Address lines for flash sizes larger than 16Meg. */
out32(GPIO0_OSRL, in32(GPIO0_OSRL) | 0x40010000);
out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40010000);
out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x40000000);
/*setup emac */
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xC080);
out32(GPIO0_TSRL, in32(GPIO0_TSRL) | 0x40);
out32(GPIO0_ISR1L, in32(GPIO0_ISR1L) | 0x55);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0x50004000);
out32(GPIO0_ISR1H, in32(GPIO0_ISR1H) | 0x00440000);
/*UART1 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0x02000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x00080000);
out32(GPIO1_ISR2L, in32(GPIO1_ISR2L) | 0x00010000);
/*setup USB 2.0 */
out32(GPIO1_TCR, in32(GPIO1_TCR) | 0xc0000000);
out32(GPIO1_OSRL, in32(GPIO1_OSRL) | 0x50000000);
out32(GPIO0_TCR, in32(GPIO0_TCR) | 0xf);
out32(GPIO0_OSRH, in32(GPIO0_OSRH) | 0xaa);
out32(GPIO0_ISR2H, in32(GPIO0_ISR2H) | 0x00000500);
/*--------------------------------------------------------------------
* Setup other serial configuration
*-------------------------------------------------------------------*/
mfsdr(sdr_pci0, reg);
mtsdr(sdr_pci0, 0x80000000 | reg); /* PCI arbiter enabled */
mtsdr(sdr_pfc0, 0x00003e00); /* Pin function */
mtsdr(sdr_pfc1, 0x00048000); /* Pin function: UART0 has 4 pins */
#if 0 /* test-only */
/*clear tmrclk divisor */
*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
/*enable ethernet */
*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
/*enable usb 1.1 fs device and remove usb 2.0 reset */
*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
/*get rid of flash write protect */
*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x40;
#endif
return 0;
}
int checkboard(void)
{
sys_info_t sysinfo;
unsigned char *s = getenv("serial#");
get_sys_info(&sysinfo);
printf("Board: Bamboo - AMCC PPC440EP Evaluation Board");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0);
}
/*************************************************************************
* sdram_init -- doesn't use serial presence detect.
*
* Assumes: 256 MB, ECC, non-registered
* PLB @ 133 MHz
*
************************************************************************/
void sdram_init(void)
{
register uint reg;
/*--------------------------------------------------------------------
* Setup some default
*------------------------------------------------------------------*/
mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram(mem_clktr, 0x40000000); /* ?? */
mtsdram(mem_wddctr, 0x40000000); /* ?? */
/*clear this first, if the DDR is enabled by a debugger
then you can not make changes. */
mtsdram(mem_cfg0, 0x00000000); /* Disable EEC */
/*--------------------------------------------------------------------
* Setup for board-specific specific mem
*------------------------------------------------------------------*/
/*
* Following for CAS Latency = 2.5 @ 133 MHz PLB
*/
mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram(mem_b1cr, 0x080a4001); /* SDBA=0x080 128MB, Mode 3, enabled */
mtsdram(mem_tr0, 0x410a4012); /* ?? */
mtsdram(mem_tr1, 0x8080080b); /* ?? */
mtsdram(mem_rtr, 0x04080000); /* ?? */
mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
mtsdram(mem_cfg0, 0x34000000); /* Disable EEC */
udelay(400); /* Delay 200 usecs (min) */
/*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/
mtsdram(mem_cfg0, 0x84000000); /* Enable */
for (;;) {
mfsdram(mem_mcsts, reg);
if (reg & 0x80000000)
break;
}
}
/*************************************************************************
* long int initdram
*
************************************************************************/
long int initdram(int board)
{
sdram_init();
return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024); /* return bytes */
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_pre_init
*
* This routine is called just prior to registering the hose and gives
* the board the opportunity to check things. Returning a value of zero
* indicates that things are bad & PCI initialization should be aborted.
*
* Different boards may wish to customize the pci controller structure
* (add regions, override default access routines, etc) or perform
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
unsigned long addr;
/*--------------------------------------------------------------------------+
* Bamboo is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
mfsdr(sdr_sdstp1, strap);
if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PAE] not set.\n");
printf("PCI: Configuration aborted.\n");
return 0;
}
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
| Set PLB3 arbiter to fair mode.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp1, addr);
mtsdr(sdr_amp1, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb3_acr);
mtdcr(plb3_acr, addr | 0x80000000);
/*-------------------------------------------------------------------------+
| Set priority for all PLB4 devices to 0.
+-------------------------------------------------------------------------*/
mfsdr(sdr_amp0, addr);
mtsdr(sdr_amp0, (addr & 0x000000FF) | 0x0000FF00);
addr = mfdcr(plb4_acr) | 0xa0000000; /* Was 0x8---- */
mtdcr(plb4_acr, addr);
/*-------------------------------------------------------------------------+
| Set Nebula PLB4 arbiter to fair mode.
+-------------------------------------------------------------------------*/
/* Segment0 */
addr = (mfdcr(plb0_acr) & ~plb0_acr_ppm_mask) | plb0_acr_ppm_fair;
addr = (addr & ~plb0_acr_hbu_mask) | plb0_acr_hbu_enabled;
addr = (addr & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep;
addr = (addr & ~plb0_acr_wrp_mask) | plb0_acr_wrp_2deep;
mtdcr(plb0_acr, addr);
/* Segment1 */
addr = (mfdcr(plb1_acr) & ~plb1_acr_ppm_mask) | plb1_acr_ppm_fair;
addr = (addr & ~plb1_acr_hbu_mask) | plb1_acr_hbu_enabled;
addr = (addr & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep;
addr = (addr & ~plb1_acr_wrp_mask) | plb1_acr_wrp_2deep;
mtdcr(plb1_acr, addr);
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
/*--------------------------------------------------------------------------+
* Set up Direct MMIO registers
*--------------------------------------------------------------------------*/
/*--------------------------------------------------------------------------+
| PowerPC440 EP PCI Master configuration.
| Map one 1Gig range of PLB/processor addresses to PCI memory space.
| PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
| Use byte reversed out routines to handle endianess.
| Make this region non-prefetchable.
+--------------------------------------------------------------------------*/
out32r(PCIX0_PMM0MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE); /* PMM0 Local Address */
out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM0PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM0MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PMM1MA, 0x00000000); /* PMM0 Mask/Attribute - disabled b4 setting */
out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
out32r(PCIX0_PMM1PCIHA, 0x00000000); /* PMM0 PCI High Address */
out32r(PCIX0_PMM1MA, 0xE0000001); /* 512M + No prefetching, and enable region */
out32r(PCIX0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
out32r(PCIX0_PTM1LA, 0); /* Local Addr. Reg */
out32r(PCIX0_PTM2MS, 0); /* Memory Size/Attribute */
out32r(PCIX0_PTM2LA, 0); /* Local Addr. Reg */
/*--------------------------------------------------------------------------+
* Set up Configuration registers
*--------------------------------------------------------------------------*/
/* Program the board's subsystem id/vendor id */
pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
CFG_PCI_SUBSYS_VENDORID);
pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
/* Configure command register as bus master */
pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
/* 240nS PCI clock */
pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
/* No error reporting */
pci_write_config_word(0, PCI_ERREN, 0);
pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/*************************************************************************
* pci_master_init
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
void pci_master_init(struct pci_controller *hose)
{
unsigned short temp_short;
/*--------------------------------------------------------------------------+
| Write the PowerPC440 EP PCI Configuration regs.
| Enable PowerPC440 EP to be a master on the PCI bus (PMM).
| Enable PowerPC440 EP to act as a PCI memory target (PTM).
+--------------------------------------------------------------------------*/
pci_read_config_word(0, PCI_COMMAND, &temp_short);
pci_write_config_word(0, PCI_COMMAND,
temp_short | PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
/*************************************************************************
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*
*
************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
/* Bamboo is always configured as host. */
return (1);
}
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* hw_watchdog_reset
*
* This routine is called to reset (keep alive) the watchdog timer
*
************************************************************************/
#if defined(CONFIG_HW_WATCHDOG)
void hw_watchdog_reset(void)
{
}
#endif
board/amcc/bamboo/config.mk 0 → 100644
View file @ 8a316c9b
#
# (C) Copyright 2002
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# esd ADCIOP boards
#
#TEXT_BASE = 0x00001000
ifeq ($(ramsym),1)
TEXT_BASE = 0xFBD00000
else
TEXT_BASE = 0xFFF80000
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif
board/amcc/bamboo/init.S 0 → 100644
View file @ 8a316c9b
/*
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <config.h>
/* General */
#define TLB_VALID 0x00000200
/* Supported page sizes */
#define SZ_1K 0x00000000
#define SZ_4K 0x00000010
#define SZ_16K 0x00000020
#define SZ_64K 0x00000030
#define SZ_256K 0x00000040
#define SZ_1M 0x00000050
#define SZ_8M 0x00000060
#define SZ_16M 0x00000070
#define SZ_256M 0x00000090
/* Storage attributes */
#define SA_W 0x00000800 /* Write-through */
#define SA_I 0x00000400 /* Caching inhibited */
#define SA_M 0x00000200 /* Memory coherence */
#define SA_G 0x00000100 /* Guarded */
#define SA_E 0x00000080 /* Endian */
/* Access control */
#define AC_X 0x00000024 /* Execute */
#define AC_W 0x00000012 /* Write */
#define AC_R 0x00000009 /* Read */
/* Some handy macros */
#define EPN(e) ((e) & 0xfffffc00)
#define TLB0(epn,sz) ( (EPN((epn)) | (sz) | TLB_VALID ) )
#define TLB1(rpn,erpn) ( ((rpn)&0xfffffc00) | (erpn) )
#define TLB2(a) ( (a)&0x00000fbf )
#define tlbtab_start\
mflr r1 ;\
bl 0f ;
#define tlbtab_end\
.long 0, 0, 0 ; \
0: mflr r0 ; \
mtlr r1 ; \
blr ;
#define tlbentry(epn,sz,rpn,erpn,attr)\
.long TLB0(epn,sz),TLB1(rpn,erpn),TLB2(attr)
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
0xf0000000 must be first, before relocation SA_I must be off to use the
dcache as stack. It is patched after relocation to enable SA_I
*/
tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
tlbentry( CFG_PCI_BASE, SZ_256M, 0xE0000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_NVRAM_BASE_ADDR, SZ_16K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
/* PCI */
tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
/* USB 2.0 Device */
tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
tlbtab_end
board/amcc/bamboo/u-boot.lds 0 → 100644
View file @ 8a316c9b
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/bamboo/init.o (.text)
cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text)
cpu/ppc4xx/serial.o (.text)
cpu/ppc4xx/cpu_init.o (.text)
cpu/ppc4xx/speed.o (.text)
cpu/ppc4xx/405gp_enet.o (.text)
common/dlmalloc.o (.text)
lib_generic/crc32.o (.text)
lib_ppc/extable.o (.text)
lib_generic/zlib.o (.text)
/* . = env_offset;*/
/* common/environment.o(.text)*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
_end = . ;
PROVIDE (end = .);
}
board/bubinga405ep/Makefile → board/amcc/bubinga/Makefile
View file @ 8a316c9b
...@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk ...@@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o OBJS = $(BOARD).o flash.o
SOBJS = init.o
$(LIB): $(OBJS) $(SOBJS) $(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $(OBJS) $(AR) crv $@ $(OBJS)
......
board/bubinga405ep/bubinga405ep.c → board/amcc/bubinga/bubinga.c
View file @ 8a316c9b
/* /*
* (C) Copyright 2000 * (C) Copyright 2000-2005
* Wolfgang Denk, DENX Software Engineering, wd@denx.de. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
* *
* See file CREDITS for list of people who contributed to this * See file CREDITS for list of people who contributed to this
...@@ -20,98 +20,65 @@ ...@@ -20,98 +20,65 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA * MA 02111-1307 USA
*/ */
long int spd_sdram (void); long int spd_sdram(void);
#include <common.h> #include <common.h>
#include <asm/processor.h> #include <asm/processor.h>
int board_early_init_f(void)
int board_early_init_f (void)
{ {
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */ mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000010); mtdcr(uiccr, 0x00000010);
mtdcr (uicpr, 0xFFFF7FF0); /* set int polarities */ mtdcr(uicpr, 0xFFFF7FF0); /* set int polarities */
mtdcr (uictr, 0x00000010); /* set int trigger levels */ mtdcr(uictr, 0x00000010); /* set int trigger levels */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
#if 0
#define mtebc(reg, data) mtdcr(ebccfga,reg);mtdcr(ebccfgd,data)
/* CS1 */
/* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
mtebc (pb1ap, 0x02815480);
mtebc (pb1cr, 0xF0018000);
p = (unsigned int*)0xEF600708;
t = *p;
t = t | 0x00000400;
*p = t;
/* BAS=0xF01,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
mtebc (pb2ap, 0x04815A80);
mtebc (pb2cr, 0xF0118000);
/* BAS=0xF02,BS=0x0(1MB),BU=0x3(R/W),BW=0x0( 8 bits) */
mtebc (pb3ap, 0x01815280);
mtebc (pb3cr, 0xF0218000);
/* BAS=0xF03,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
mtebc (pb7ap, 0x01815280);
mtebc (pb7cr, 0xF0318000);
/* set UART1 control to select CTS/RTS */
#define FPGA_BRDC 0xF0300004
*(volatile char *) (FPGA_BRDC) |= 0x1;
#endif
return 0; return 0;
} }
/* ------------------------------------------------------------------------- */
/* /*
* Check Board Identity: * Check Board Identity:
*/ */
int checkboard(void)
int checkboard (void)
{ {
unsigned char *s = getenv ("serial#"); unsigned char *s = getenv("serial#");
puts ("Board: IBM 405EP Eval Board"); puts("Board: Bubinga - AMCC PPC405EP Evaluation Board");
if (s != NULL) { if (s != NULL) {
puts (", serial# "); puts(", serial# ");
puts (s); puts(s);
} }
putc ('\n'); putc('\n');
return (0); return (0);
} }
/*
* sdram_init - Dummy implementation for start.S, spd_sdram used on this board!
*/
void sdram_init(void)
{
return;
}
/* ------------------------------------------------------------------------- /* -------------------------------------------------------------------------
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration the necessary info for SDRAM controller configuration
------------------------------------------------------------------------- */ ------------------------------------------------------------------------- */
long int initdram (int board_type) long int initdram(int board_type)
{ {
long int ret; long int ret;
ret = spd_sdram (); ret = spd_sdram();
return ret; return ret;
} }
/* ------------------------------------------------------------------------- */ int testdram(void)
int testdram (void)
{ {
/* TODO: XXX XXX XXX */ /* TODO: XXX XXX XXX */
printf ("test: xxx MB - ok\n"); printf("test: xxx MB - ok\n");
return (0); return (0);
} }
/* ------------------------------------------------------------------------- */
board/walnut405/config.mk → board/amcc/bubinga/config.mk
View file @ 8a316c9b
...@@ -21,9 +21,4 @@ ...@@ -21,9 +21,4 @@
# MA 02111-1307 USA # MA 02111-1307 USA
# #
# TEXT_BASE = 0xFFFC0000
# esd ADCIOP boards
#
#TEXT_BASE = 0xFFFE0000
TEXT_BASE = 0xFFF80000
board/amcc/bubinga/flash.c 0 → 100644
View file @ 8a316c9b
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
/*
* include common flash code (for amcc boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static void flash_get_offsets(ulong base, flash_info_t * info);
unsigned long flash_init(void)
{
unsigned long size_b0, size_b1;
int i;
uint pbcr;
unsigned long base_b0, base_b1;
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
}
/* Static FLASH Bank configuration here - FIXME XXX */
size_b0 =
flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
if (flash_info[0].flash_id == FLASH_UNKNOWN) {
printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
size_b0, size_b0 << 20);
}
/* Only one bank */
if (CFG_MAX_FLASH_BANKS == 1) {
/* Setup offsets */
flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
&flash_info[0]);
#ifdef CFG_ENV_IS_IN_FLASH
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[0]);
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
&flash_info[0]);
#endif
size_b1 = 0;
flash_info[0].size = size_b0;
}
/* 2 banks */
else {
size_b1 =
flash_get_size((vu_long *) FLASH_BASE1_PRELIM,
&flash_info[1]);
/* Re-do sizing to get full correct info */
if (size_b1) {
mtdcr(ebccfga, pb0cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb0cr);
base_b1 = -size_b1;
pbcr = (pbcr & 0x0001ffff) | base_b1 |
(((size_b1 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb1cr = %x\n", pbcr); */
}
if (size_b0) {
mtdcr(ebccfga, pb1cr);
pbcr = mfdcr(ebccfgd);
mtdcr(ebccfga, pb1cr);
base_b0 = base_b1 - size_b0;
pbcr = (pbcr & 0x0001ffff) | base_b0 |
(((size_b0 / 1024 / 1024) - 1) << 17);
mtdcr(ebccfgd, pbcr);
/* printf("pb0cr = %x\n", pbcr); */
}
size_b0 = flash_get_size((vu_long *) base_b0, &flash_info[0]);
flash_get_offsets(base_b0, &flash_info[0]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b0 + size_b0 - CFG_MONITOR_LEN,
base_b0 + size_b0 - 1, &flash_info[0]);
/* Also protect sector containing initial power-up instruction */
/* (flash_protect() checks address range - other call ignored) */
(void)flash_protect(FLAG_PROTECT_SET,
0xFFFFFFFC, 0xFFFFFFFF, &flash_info[0]);
(void)flash_protect(FLAG_PROTECT_SET,
0xFFFFFFFC, 0xFFFFFFFF, &flash_info[1]);
if (size_b1) {
/* Re-do sizing to get full correct info */
size_b1 =
flash_get_size((vu_long *) base_b1, &flash_info[1]);
flash_get_offsets(base_b1, &flash_info[1]);
/* monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
base_b1 + size_b1 - CFG_MONITOR_LEN,
base_b1 + size_b1 - 1,
&flash_info[1]);
/* monitor protection OFF by default (one is enough) */
(void)flash_protect(FLAG_PROTECT_CLEAR,
base_b0 + size_b0 - CFG_MONITOR_LEN,
base_b0 + size_b0 - 1,
&flash_info[0]);
} else {
flash_info[1].flash_id = FLASH_UNKNOWN;
flash_info[1].sector_count = -1;
}
flash_info[0].size = size_b0;
flash_info[1].size = size_b1;
} /* else 2 banks */
return (size_b0 + size_b1);
}
static void flash_get_offsets(ulong base, flash_info_t * info)
{
int i;
/* set up sector start address table */
if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) ||
(info->flash_id == FLASH_AM040)) {
for (i = 0; i < info->sector_count; i++)
info->start[i] = base + (i * 0x00010000);
} else {
if (info->flash_id & FLASH_BTYPE) {
/* set sector offsets for bottom boot block type */
info->start[0] = base + 0x00000000;
info->start[1] = base + 0x00004000;
info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) {
info->start[i] =
base + (i * 0x00010000) - 0x00030000;
}
} else {
/* set sector offsets for top boot block type */
i = info->sector_count - 1;
info->start[i--] = base + info->size - 0x00004000;
info->start[i--] = base + info->size - 0x00006000;
info->start[i--] = base + info->size - 0x00008000;
for (; i >= 0; i--) {
info->start[i] = base + i * 0x00010000;
}
}
}
}
board/bubinga405ep/u-boot.lds → board/amcc/bubinga/u-boot.lds
View file @ 8a316c9b
...@@ -62,7 +62,6 @@ SECTIONS ...@@ -62,7 +62,6 @@ SECTIONS
/* the sector layout of our flash chips! XXX FIXME XXX */ /* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text) cpu/ppc4xx/start.o (.text)
board/bubinga405ep/init.o (.text)
cpu/ppc4xx/kgdb.o (.text) cpu/ppc4xx/kgdb.o (.text)
cpu/ppc4xx/traps.o (.text) cpu/ppc4xx/traps.o (.text)
cpu/ppc4xx/interrupts.o (.text) cpu/ppc4xx/interrupts.o (.text)
......
board/ocotea/flash.c → board/amcc/common/flash.c
View file @ 8a316c9b
...@@ -35,115 +35,13 @@ ...@@ -35,115 +35,13 @@
#include <ppc4xx.h> #include <ppc4xx.h>
#include <asm/processor.h> #include <asm/processor.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
#define BOOT_SMALL_FLASH 0x40 /* 01000000 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define BOOT_SMALL_FLASH_VAL 4
#define FLASH_ONBD_N_VAL 2
#define FLASH_SRAM_SEL_VAL 1
flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
{0xFF800000, 0xFF880000, 0xFFC00000}, /* 0:000: configuraton 4 */
{0xFF900000, 0xFF980000, 0xFFC00000}, /* 1:001: configuraton 3 */
{0x00000000, 0x00000000, 0x00000000}, /* 2:010: configuraton 8 */
{0x00000000, 0x00000000, 0x00000000}, /* 3:011: configuraton 7 */
{0xFFE00000, 0xFFF00000, 0xFF800000}, /* 4:100: configuraton 2 */
{0xFFF00000, 0xFFF80000, 0xFF800000}, /* 5:101: configuraton 1 */
{0x00000000, 0x00000000, 0x00000000}, /* 6:110: configuraton 6 */
{0x00000000, 0x00000000, 0x00000000} /* 7:111: configuraton 5 */
};
/*----------------------------------------------------------------------- /*-----------------------------------------------------------------------
* Functions * Functions
*/ */
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
static int write_word(flash_info_t * info, ulong dest, ulong data); static int write_word(flash_info_t * info, ulong dest, ulong data);
#ifdef CONFIG_OCOTEA
#define ADDR0 0x5555
#define ADDR1 0x2aaa
#define FLASH_WORD_SIZE unsigned char
#endif
/*-----------------------------------------------------------------------
*/
unsigned long flash_init(void)
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
unsigned char switch_status;
unsigned short index = 0;
int i;
/* read FPGA base register FPGA_REG0 */
switch_status = *fpga_base;
/* check the bitmap of switch status */
if (switch_status & BOOT_SMALL_FLASH) {
index += BOOT_SMALL_FLASH_VAL;
}
if (switch_status & FLASH_ONBD_N) {
index += FLASH_ONBD_N_VAL;
}
if (switch_status & FLASH_SRAM_SEL) {
index += FLASH_SRAM_SEL_VAL;
}
DEBUGF("\n");
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
/* check whether the address is 0 */
if (flash_addr_table[index][i] == 0) {
continue;
}
/* call flash_get_size() to initialize sector address */
size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], &flash_info[i]);
flash_info[i].size = size_b[i];
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i] << 20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
total_b += flash_info[i].size;
}
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET,
-CFG_MONITOR_LEN,
0xffffffff,
&flash_info[2]);
return total_b;
}
/*-----------------------------------------------------------------------
*/
void flash_print_info(flash_info_t * info) void flash_print_info(flash_info_t * info)
{ {
int i; int i;
...@@ -191,6 +89,9 @@ void flash_print_info(flash_info_t * info) ...@@ -191,6 +89,9 @@ void flash_print_info(flash_info_t * info)
case FLASH_AM800T: case FLASH_AM800T:
printf("AM29LV800T (8 Mbit, top boot sector)\n"); printf("AM29LV800T (8 Mbit, top boot sector)\n");
break; break;
case FLASH_AMD016:
printf("AM29F016D (16 Mbit, uniform sector size)\n");
break;
case FLASH_AM160B: case FLASH_AM160B:
printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
break; break;
...@@ -203,7 +104,7 @@ void flash_print_info(flash_info_t * info) ...@@ -203,7 +104,7 @@ void flash_print_info(flash_info_t * info)
case FLASH_AM320T: case FLASH_AM320T:
printf("AM29LV320T (32 Mbit, top boot sector)\n"); printf("AM29LV320T (32 Mbit, top boot sector)\n");
break; break;
case FLASH_AMDLV033C: case FLASH_AM033C:
printf("AM29LV033C (32 Mbit, top boot sector)\n"); printf("AM29LV033C (32 Mbit, top boot sector)\n");
break; break;
case FLASH_SST800A: case FLASH_SST800A:
...@@ -230,7 +131,7 @@ void flash_print_info(flash_info_t * info) ...@@ -230,7 +131,7 @@ void flash_print_info(flash_info_t * info)
else else
size = info->start[0] + info->size - info->start[i]; size = info->start[0] + info->size - info->start[i];
erased = 1; erased = 1;
flash = (volatile unsigned long *) info->start[i]; flash = (volatile unsigned long *)info->start[i];
size = size >> 2; /* divide by 4 for longword access */ size = size >> 2; /* divide by 4 for longword access */
for (k = 0; k < size; k++) { for (k = 0; k < size; k++) {
if (*flash++ != 0xffffffff) { if (*flash++ != 0xffffffff) {
...@@ -249,8 +150,6 @@ void flash_print_info(flash_info_t * info) ...@@ -249,8 +150,6 @@ void flash_print_info(flash_info_t * info)
return; return;
} }
/*-----------------------------------------------------------------------
*/
/* /*
* The following code cannot be run from FLASH! * The following code cannot be run from FLASH!
...@@ -258,72 +157,115 @@ void flash_print_info(flash_info_t * info) ...@@ -258,72 +157,115 @@ void flash_print_info(flash_info_t * info)
static ulong flash_get_size(vu_long * addr, flash_info_t * info) static ulong flash_get_size(vu_long * addr, flash_info_t * info)
{ {
short i; short i;
FLASH_WORD_SIZE value; CFG_FLASH_WORD_SIZE value;
ulong base = (ulong) addr; ulong base = (ulong) addr;
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) addr; volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
DEBUGF("FLASH ADDR: %08x\n", (unsigned) addr); DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
/* Write auto select command: read Manufacturer ID */ /* Write auto select command: read Manufacturer ID */
udelay(10000); addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
udelay(1000); addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055;
udelay(1000);
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00900090;
udelay(1000); udelay(1000);
value = addr2[0]; value = addr2[0];
DEBUGF("FLASH MANUFACT: %x\n", value); DEBUGF("FLASH MANUFACT: %x\n", value);
switch (value) { switch (value) {
case (FLASH_WORD_SIZE) AMD_MANUFACT: case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
info->flash_id = FLASH_MAN_AMD; info->flash_id = FLASH_MAN_AMD;
break; break;
case (FLASH_WORD_SIZE) FUJ_MANUFACT: case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
info->flash_id = FLASH_MAN_FUJ; info->flash_id = FLASH_MAN_FUJ;
break; break;
case (FLASH_WORD_SIZE) SST_MANUFACT: case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
info->flash_id = FLASH_MAN_SST; info->flash_id = FLASH_MAN_SST;
break; break;
case (FLASH_WORD_SIZE) STM_MANUFACT: case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
info->flash_id = FLASH_MAN_STM; info->flash_id = FLASH_MAN_STM;
break; break;
default: default:
info->flash_id = FLASH_UNKNOWN; info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0; info->sector_count = 0;
info->size = 0; info->size = 0;
return (0); /* no or unknown flash */ return (0); /* no or unknown flash */
} }
value = addr2[1]; /* device ID */ value = addr2[1]; /* device ID */
DEBUGF("\nFLASH DEVICEID: %x\n", value); DEBUGF("\nFLASH DEVICEID: %x\n", value);
switch (value) { switch (value) {
case (FLASH_WORD_SIZE) AMD_ID_LV040B: case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
info->flash_id += FLASH_AM040; info->flash_id += FLASH_AM040;
info->sector_count = 8; info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */ info->size = 0x0080000; /* => 512 ko */
break; break;
case (FLASH_WORD_SIZE) AMD_ID_F040B:
case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
info->flash_id += FLASH_AM040; info->flash_id += FLASH_AM040;
info->sector_count = 8; info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */ info->size = 0x0080000; /* => 512 ko */
break; break;
case (FLASH_WORD_SIZE) STM_ID_M29W040B:
case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
info->flash_id += FLASH_AM040; info->flash_id += FLASH_AM040;
info->sector_count = 8; info->sector_count = 8;
info->size = 0x0080000; /* => 512 ko */ info->size = 0x0080000; /* => 512 ko */
break; break;
case (FLASH_WORD_SIZE) AMD_ID_LV033C:
case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
info->flash_id += FLASH_AMD016;
info->sector_count = 32;
info->size = 0x00200000;
break; /* => 2 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
info->flash_id += FLASH_AMDLV033C; info->flash_id += FLASH_AMDLV033C;
info->sector_count = 64; info->sector_count = 64;
info->size = 0x00400000; info->size = 0x00400000;
break; /* => 4 MB */ break; /* => 4 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
info->flash_id += FLASH_AM400T;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
info->flash_id += FLASH_AM400B;
info->sector_count = 11;
info->size = 0x00080000;
break; /* => 0.5 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
info->flash_id += FLASH_AM800T;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
info->flash_id += FLASH_AM800B;
info->sector_count = 19;
info->size = 0x00100000;
break; /* => 1 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
info->flash_id += FLASH_AM160T;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
info->flash_id += FLASH_AM160B;
info->sector_count = 35;
info->size = 0x00200000;
break; /* => 2 MB */
default: default:
info->flash_id = FLASH_UNKNOWN; info->flash_id = FLASH_UNKNOWN;
return (0); /* => no or unknown flash */ return (0); /* => no or unknown flash */
} }
/* set up sector start address table */ /* set up sector start address table */
...@@ -340,7 +282,8 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) ...@@ -340,7 +282,8 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
info->start[2] = base + 0x00006000; info->start[2] = base + 0x00006000;
info->start[3] = base + 0x00008000; info->start[3] = base + 0x00008000;
for (i = 4; i < info->sector_count; i++) { for (i = 4; i < info->sector_count; i++) {
info->start[i] = base + (i * 0x00010000) - 0x00030000; info->start[i] =
base + (i * 0x00010000) - 0x00030000;
} }
} else { } else {
/* set sector offsets for top boot block type */ /* set sector offsets for top boot block type */
...@@ -358,14 +301,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) ...@@ -358,14 +301,14 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
for (i = 0; i < info->sector_count; i++) { for (i = 0; i < info->sector_count; i++) {
/* read sector protection at sector address, (A7 .. A0) = 0x02 */ /* read sector protection at sector address, (A7 .. A0) = 0x02 */
/* D0 = 1 if protected */ /* D0 = 1 if protected */
addr2 = (volatile FLASH_WORD_SIZE *) (info->start[i]); addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
/* For AMD29033C flash we need to resend the command of * /* For AMD29033C flash we need to resend the command of *
* reading flash protection for upper 8 Mb of flash */ * reading flash protection for upper 8 Mb of flash */
if ( i == 32 ) { if (i == 32) {
addr2[ADDR0] = (FLASH_WORD_SIZE) 0xAAAAAAAA; addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x55555555; addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x90909090; addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
} }
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
...@@ -375,14 +318,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) ...@@ -375,14 +318,7 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
} }
/* issue bank reset to return to read mode */ /* issue bank reset to return to read mode */
addr2[0] = (FLASH_WORD_SIZE) 0x00F000F0; addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
/*
* Prevent writes to uninitialized FLASH.
*/
if (info->flash_id != FLASH_UNKNOWN) {
/* ? ? ? */
}
return (info->size); return (info->size);
} }
...@@ -390,13 +326,13 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info) ...@@ -390,13 +326,13 @@ static ulong flash_get_size(vu_long * addr, flash_info_t * info)
int wait_for_DQ7(flash_info_t * info, int sect) int wait_for_DQ7(flash_info_t * info, int sect)
{ {
ulong start, now, last; ulong start, now, last;
volatile FLASH_WORD_SIZE *addr = volatile CFG_FLASH_WORD_SIZE *addr =
(FLASH_WORD_SIZE *) (info->start[sect]); (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
start = get_timer(0); start = get_timer(0);
last = start; last = start;
while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) != while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
(FLASH_WORD_SIZE) 0x00800080) { (CFG_FLASH_WORD_SIZE) 0x00800080) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf("Timeout\n"); printf("Timeout\n");
return -1; return -1;
...@@ -410,13 +346,10 @@ int wait_for_DQ7(flash_info_t * info, int sect) ...@@ -410,13 +346,10 @@ int wait_for_DQ7(flash_info_t * info, int sect)
return 0; return 0;
} }
/*-----------------------------------------------------------------------
*/
int flash_erase(flash_info_t * info, int s_first, int s_last) int flash_erase(flash_info_t * info, int s_first, int s_last)
{ {
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]); volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
volatile FLASH_WORD_SIZE *addr2; volatile CFG_FLASH_WORD_SIZE *addr2;
int flag, prot, sect, l_sect; int flag, prot, sect, l_sect;
int i; int i;
...@@ -456,24 +389,24 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) ...@@ -456,24 +389,24 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
/* Start erase on unprotected sectors */ /* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) { for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */ if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]); addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (FLASH_WORD_SIZE) 0x00500050; /* block erase */ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */
for (i = 0; i < 50; i++) for (i = 0; i < 50; i++)
udelay(1000); /* wait 1 ms */ udelay(1000); /* wait 1 ms */
} else { } else {
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00800080; addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
addr[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[0] = (FLASH_WORD_SIZE) 0x00300030; /* sector erase */ addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */
} }
l_sect = sect; l_sect = sect;
/* /*
...@@ -495,8 +428,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last) ...@@ -495,8 +428,8 @@ int flash_erase(flash_info_t * info, int s_first, int s_last)
udelay(1000); udelay(1000);
/* reset to read mode */ /* reset to read mode */
addr = (FLASH_WORD_SIZE *) info->start[0]; addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
addr[0] = (FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */
printf(" done\n"); printf(" done\n");
return 0; return 0;
...@@ -513,29 +446,29 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) ...@@ -513,29 +446,29 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
ulong cp, wp, data; ulong cp, wp, data;
int i, l, rc; int i, l, rc;
wp = (addr & ~3); /* get lower word aligned address */ wp = (addr & ~3); /* get lower word aligned address */
/* /*
* handle unaligned start bytes * handle unaligned start bytes
*/ */
if ((l = addr - wp) != 0) { if ((l = addr - wp) != 0) {
data = 0; data = 0;
for (i = 0, cp = wp; i < l; ++i, ++cp) { for (i = 0, cp = wp; i < l; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp); data = (data << 8) | (*(uchar *) cp);
} }
for (; i < 4 && cnt > 0; ++i) { for (; i < 4 && cnt > 0; ++i) {
data = (data << 8) | *src++; data = (data << 8) | *src++;
--cnt; --cnt;
++cp; ++cp;
} }
for (; cnt == 0 && i < 4; ++i, ++cp) { for (; cnt == 0 && i < 4; ++i, ++cp) {
data = (data << 8) | (*(uchar *) cp); data = (data << 8) | (*(uchar *) cp);
} }
if ((rc = write_word(info, wp, data)) != 0) { if ((rc = write_word(info, wp, data)) != 0) {
return (rc); return (rc);
} }
wp += 4; wp += 4;
} }
/* /*
...@@ -580,27 +513,26 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) ...@@ -580,27 +513,26 @@ int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
*/ */
static int write_word(flash_info_t * info, ulong dest, ulong data) static int write_word(flash_info_t * info, ulong dest, ulong data)
{ {
volatile FLASH_WORD_SIZE *addr2 = (FLASH_WORD_SIZE *) (info->start[0]); volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
volatile FLASH_WORD_SIZE *dest2 = (FLASH_WORD_SIZE *) dest; volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
volatile FLASH_WORD_SIZE *data2 = (FLASH_WORD_SIZE *) & data; volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
ulong start; ulong start;
int i; int i;
/* Check if Flash is (sufficiently) erased */ /* Check if Flash is (sufficiently) erased */
if ((*((volatile FLASH_WORD_SIZE *) dest) & if ((*((vu_long *)dest) & data) != data) {
(FLASH_WORD_SIZE) data) != (FLASH_WORD_SIZE) data) {
return (2); return (2);
} }
for (i = 0; i < 4 / sizeof(FLASH_WORD_SIZE); i++) { for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
int flag; int flag;
/* Disable interrupts which might cause a timeout here */ /* Disable interrupts which might cause a timeout here */
flag = disable_interrupts(); flag = disable_interrupts();
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00AA00AA; addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
addr2[ADDR1] = (FLASH_WORD_SIZE) 0x00550055; addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
addr2[ADDR0] = (FLASH_WORD_SIZE) 0x00A000A0; addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
dest2[i] = data2[i]; dest2[i] = data2[i];
...@@ -610,8 +542,8 @@ static int write_word(flash_info_t * info, ulong dest, ulong data) ...@@ -610,8 +542,8 @@ static int write_word(flash_info_t * info, ulong dest, ulong data)
/* data polling for D7 */ /* data polling for D7 */
start = get_timer(0); start = get_timer(0);
while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) != while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
(data2[i] & (FLASH_WORD_SIZE) 0x00800080)) { (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
return (1); return (1);
......
board/ebony/config.mk → board/amcc/ebony/config.mk
View file @ 8a316c9b
...@@ -30,7 +30,7 @@ ...@@ -30,7 +30,7 @@
ifeq ($(ramsym),1) ifeq ($(ramsym),1)
TEXT_BASE = 0x07FD0000 TEXT_BASE = 0x07FD0000
else else
TEXT_BASE = 0xFFF80000 TEXT_BASE = 0xFFFC0000
endif endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1 PLATFORM_CPPFLAGS += -DCONFIG_440=1
......
board/ebony/ebony.c → board/amcc/ebony/ebony.c
View file @ 8a316c9b
...@@ -20,9 +20,7 @@ ...@@ -20,9 +20,7 @@
* MA 02111-1307 USA * MA 02111-1307 USA
*/ */
#include <common.h> #include <common.h>
#include "ebony.h"
#include <asm/processor.h> #include <asm/processor.h>
#include <spd_sdram.h> #include <spd_sdram.h>
...@@ -30,99 +28,102 @@ ...@@ -30,99 +28,102 @@
#define FLASH_ONBD_N 2 /* 00000010 */ #define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */ #define FLASH_SRAM_SEL 1 /* 00000001 */
long int fixed_sdram (void); long int fixed_sdram(void);
int board_early_init_f (void) int board_early_init_f(void)
{ {
uint reg; uint reg;
unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE; unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
unsigned char status; unsigned char status;
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Setup the external bus controller/chip selects * Setup the external bus controller/chip selects
*-------------------------------------------------------------------*/ *-------------------------------------------------------------------*/
mtdcr (ebccfga, xbcfg); mtdcr(ebccfga, xbcfg);
reg = mfdcr (ebccfgd); reg = mfdcr(ebccfgd);
mtdcr (ebccfgd, reg | 0x04000000); /* Set ATC */ mtdcr(ebccfgd, reg | 0x04000000); /* Set ATC */
mtebc (pb1ap, 0x02815480); /* NVRAM/RTC */ mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
mtebc (pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
mtebc (pb7ap, 0x01015280); /* FPGA registers */ mtebc(pb7ap, 0x01015280); /* FPGA registers */
mtebc (pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
/* read FPGA_REG0 and set the bus controller */ /* read FPGA_REG0 and set the bus controller */
status = *fpga_base; status = *fpga_base;
if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) { if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
mtebc (pb0ap, 0x9b015480); /* FLASH/SRAM */ mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
mtebc (pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
mtebc (pb2ap, 0x9b015480); /* 4MB FLASH */ mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
mtebc (pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
} else { } else {
mtebc (pb0ap, 0x9b015480); /* 4MB FLASH */ mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
mtebc (pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
/* set CS2 if FLASH_ONBD_N == 0 */ /* set CS2 if FLASH_ONBD_N == 0 */
if (!(status & FLASH_ONBD_N)) { if (!(status & FLASH_ONBD_N)) {
mtebc (pb2ap, 0x9b015480); /* FLASH/SRAM */ mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
mtebc (pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
} }
} }
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Setup the interrupt controller polarities, triggers, etc. * Setup the interrupt controller polarities, triggers, etc.
*-------------------------------------------------------------------*/ *-------------------------------------------------------------------*/
mtdcr (uic0sr, 0xffffffff); /* clear all */ mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr (uic0er, 0x00000000); /* disable all */ mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr (uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */ mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
mtdcr (uic0pr, 0xfffffe13); /* per ref-board manual */ mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
mtdcr (uic0tr, 0x01c00008); /* per ref-board manual */ mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
mtdcr (uic0vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic0sr, 0xffffffff); /* clear all */ mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr (uic1er, 0x00000000); /* disable all */ mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr (uic1cr, 0x00000000); /* all non-critical */ mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr (uic1pr, 0xffffe0ff); /* per ref-board manual */ mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
mtdcr (uic1tr, 0x00ffc000); /* per ref-board manual */ mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
mtdcr (uic1vr, 0x00000001); /* int31 highest, base=0x000 */ mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
mtdcr (uic1sr, 0xffffffff); /* clear all */ mtdcr(uic1sr, 0xffffffff); /* clear all */
return 0; return 0;
} }
int checkboard(void)
int checkboard (void)
{ {
sys_info_t sysinfo; sys_info_t sysinfo;
unsigned char *s = getenv("serial#");
get_sys_info (&sysinfo); get_sys_info(&sysinfo);
printf ("Board: IBM 440GP Evaluation Board (Ebony)\n"); printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
printf ("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000); if (s != NULL) {
printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000); puts(", serial# ");
printf ("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000); puts(s);
printf ("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000); }
printf ("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000); putc('\n');
printf("\tVCO: %lu MHz\n", sysinfo.freqVCOMhz / 1000000);
printf("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
printf("\tPLB: %lu MHz\n", sysinfo.freqPLB / 1000000);
printf("\tOPB: %lu MHz\n", sysinfo.freqOPB / 1000000);
printf("\tEPB: %lu MHz\n", sysinfo.freqEPB / 1000000);
return (0); return (0);
} }
long int initdram(int board_type)
long int initdram (int board_type)
{ {
long dram_size = 0; long dram_size = 0;
#if defined(CONFIG_SPD_EEPROM) #if defined(CONFIG_SPD_EEPROM)
dram_size = spd_sdram (0); dram_size = spd_sdram(0);
#else #else
dram_size = fixed_sdram (); dram_size = fixed_sdram();
#endif #endif
return dram_size; return dram_size;
} }
#if defined(CFG_DRAM_TEST) #if defined(CFG_DRAM_TEST)
int testdram (void) int testdram(void)
{ {
uint *pstart = (uint *) 0x00000000; uint *pstart = (uint *) 0x00000000;
uint *pend = (uint *) 0x08000000; uint *pend = (uint *) 0x08000000;
...@@ -133,7 +134,7 @@ int testdram (void) ...@@ -133,7 +134,7 @@ int testdram (void)
for (p = pstart; p < pend; p++) { for (p = pstart; p < pend; p++) {
if (*p != 0xaaaaaaaa) { if (*p != 0xaaaaaaaa) {
printf ("SDRAM test fails at: %08x\n", (uint) p); printf("SDRAM test fails at: %08x\n", (uint) p);
return 1; return 1;
} }
} }
...@@ -143,7 +144,7 @@ int testdram (void) ...@@ -143,7 +144,7 @@ int testdram (void)
for (p = pstart; p < pend; p++) { for (p = pstart; p < pend; p++) {
if (*p != 0x55555555) { if (*p != 0x55555555) {
printf ("SDRAM test fails at: %08x\n", (uint) p); printf("SDRAM test fails at: %08x\n", (uint) p);
return 1; return 1;
} }
} }
...@@ -159,18 +160,18 @@ int testdram (void) ...@@ -159,18 +160,18 @@ int testdram (void)
* PLB @ 133 MHz * PLB @ 133 MHz
* *
************************************************************************/ ************************************************************************/
long int fixed_sdram (void) long int fixed_sdram(void)
{ {
uint reg; uint reg;
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Setup some default * Setup some default
*------------------------------------------------------------------*/ *------------------------------------------------------------------*/
mtsdram (mem_uabba, 0x00000000); /* ubba=0 (default) */ mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
mtsdram (mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
mtsdram (mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */ mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
mtsdram (mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */ mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
mtsdram (mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Setup for board-specific specific mem * Setup for board-specific specific mem
...@@ -178,28 +179,27 @@ long int fixed_sdram (void) ...@@ -178,28 +179,27 @@ long int fixed_sdram (void)
/* /*
* Following for CAS Latency = 2.5 @ 133 MHz PLB * Following for CAS Latency = 2.5 @ 133 MHz PLB
*/ */
mtsdram (mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
mtsdram (mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
/* RA=10 RD=3 */ /* RA=10 RD=3 */
mtsdram (mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
mtsdram (mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
mtsdram (mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */ mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
udelay (400); /* Delay 200 usecs (min) */ udelay(400); /* Delay 200 usecs (min) */
/*-------------------------------------------------------------------- /*--------------------------------------------------------------------
* Enable the controller, then wait for DCEN to complete * Enable the controller, then wait for DCEN to complete
*------------------------------------------------------------------*/ *------------------------------------------------------------------*/
mtsdram (mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
for (;;) { for (;;) {
mfsdram (mem_mcsts, reg); mfsdram(mem_mcsts, reg);
if (reg & 0x80000000) if (reg & 0x80000000)
break; break;
} }
return (128 * 1024 * 1024); /* 128 MB */ return (128 * 1024 * 1024); /* 128 MB */
} }
#endif /* !defined(CONFIG_SPD_EEPROM) */ #endif /* !defined(CONFIG_SPD_EEPROM) */
/************************************************************************* /*************************************************************************
* pci_pre_init * pci_pre_init
...@@ -214,23 +214,23 @@ long int fixed_sdram (void) ...@@ -214,23 +214,23 @@ long int fixed_sdram (void)
* *
************************************************************************/ ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) #if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller * hose ) int pci_pre_init(struct pci_controller *hose)
{ {
unsigned long strap; unsigned long strap;
/*--------------------------------------------------------------------------+ /*--------------------------------------------------------------------------+
* The ebony board is always configured as the host & requires the * The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled. * PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/ *--------------------------------------------------------------------------*/
strap = mfdcr(cpc0_strp1); strap = mfdcr(cpc0_strp1);
if( (strap & 0x00100000) == 0 ){ if ((strap & 0x00100000) == 0) {
printf("PCI: CPC0_STRP1[PAE] not set.\n"); printf("PCI: CPC0_STRP1[PAE] not set.\n");
return 0; return 0;
} }
return 1; return 1;
} }
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */ #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
/************************************************************************* /*************************************************************************
* pci_target_init * pci_target_init
...@@ -241,38 +241,37 @@ int pci_pre_init(struct pci_controller * hose ) ...@@ -241,38 +241,37 @@ int pci_pre_init(struct pci_controller * hose )
* *
************************************************************************/ ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose ) void pci_target_init(struct pci_controller *hose)
{ {
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/*--------------------------------------------------------------------------+ /*--------------------------------------------------------------------------+
* Disable everything * Disable everything
*--------------------------------------------------------------------------*/ *--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0SA, 0 ); /* disable */ out32r(PCIX0_PIM0SA, 0); /* disable */
out32r( PCIX0_PIM1SA, 0 ); /* disable */ out32r(PCIX0_PIM1SA, 0); /* disable */
out32r( PCIX0_PIM2SA, 0 ); /* disable */ out32r(PCIX0_PIM2SA, 0); /* disable */
out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
/*--------------------------------------------------------------------------+ /*--------------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
* options to not support sizes such as 128/256 MB. * options to not support sizes such as 128/256 MB.
*--------------------------------------------------------------------------*/ *--------------------------------------------------------------------------*/
out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
out32r( PCIX0_PIM0LAH, 0 ); out32r(PCIX0_PIM0LAH, 0);
out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
out32r( PCIX0_BAR0, 0 ); out32r(PCIX0_BAR0, 0);
/*--------------------------------------------------------------------------+ /*--------------------------------------------------------------------------+
* Program the board's subsystem id/vendor id * Program the board's subsystem id/vendor id
*--------------------------------------------------------------------------*/ *--------------------------------------------------------------------------*/
out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
} }
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
/************************************************************************* /*************************************************************************
* is_pci_host * is_pci_host
...@@ -292,7 +291,7 @@ void pci_target_init(struct pci_controller * hose ) ...@@ -292,7 +291,7 @@ void pci_target_init(struct pci_controller * hose )
#if defined(CONFIG_PCI) #if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose) int is_pci_host(struct pci_controller *hose)
{ {
/* The ebony board is always configured as host. */ /* The ebony board is always configured as host. */
return(1); return (1);
} }
#endif /* defined(CONFIG_PCI) */ #endif /* defined(CONFIG_PCI) */
board/amcc/ebony/flash.c 0 → 100644
View file @ 8a316c9b
/*
* (C) Copyright 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002 Jun Gu <jung@artesyncp.com>
* Add support for Am29F016D and dynamic switch setting.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*
* Modified 4/5/2001
* Wait for completion of each sector erase command issued
* 4/5/2001
* Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com
*/
#include <common.h>
#include <ppc4xx.h>
#include <asm/processor.h>
#undef DEBUG
#ifdef DEBUG
#define DEBUGF(x...) printf(x)
#else
#define DEBUGF(x...)
#endif /* DEBUG */
#define BOOT_SMALL_FLASH 32 /* 00100000 */
#define FLASH_ONBD_N 2 /* 00000010 */
#define FLASH_SRAM_SEL 1 /* 00000001 */
#define BOOT_SMALL_FLASH_VAL 4
#define FLASH_ONBD_N_VAL 2
#define FLASH_SRAM_SEL_VAL 1
static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
{0xffc00000, 0xffe00000, 0xff880000}, /* 0:000: configuraton 3 */
{0xffc00000, 0xffe00000, 0xff800000}, /* 1:001: configuraton 4 */
{0xffc00000, 0xffe00000, 0x00000000}, /* 2:010: configuraton 7 */
{0xffc00000, 0xffe00000, 0x00000000}, /* 3:011: configuraton 8 */
{0xff800000, 0xffa00000, 0xfff80000}, /* 4:100: configuraton 1 */
{0xff800000, 0xffa00000, 0xfff00000}, /* 5:101: configuraton 2 */
{0xffc00000, 0xffe00000, 0x00000000}, /* 6:110: configuraton 5 */
{0xffc00000, 0xffe00000, 0x00000000} /* 7:111: configuraton 6 */
};
/*
* include common flash code (for amcc boards)
*/
#include "../common/flash.c"
/*-----------------------------------------------------------------------
* Functions
*/
static ulong flash_get_size(vu_long * addr, flash_info_t * info);
unsigned long flash_init(void)
{
unsigned long total_b = 0;
unsigned long size_b[CFG_MAX_FLASH_BANKS];
unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
unsigned char switch_status;
unsigned short index = 0;
int i;
/* read FPGA base register FPGA_REG0 */
switch_status = *fpga_base;
/* check the bitmap of switch status */
if (switch_status & BOOT_SMALL_FLASH) {
index += BOOT_SMALL_FLASH_VAL;
}
if (switch_status & FLASH_ONBD_N) {
index += FLASH_ONBD_N_VAL;
}
if (switch_status & FLASH_SRAM_SEL) {
index += FLASH_SRAM_SEL_VAL;
}
DEBUGF("\n");
DEBUGF("FLASH: Index: %d\n", index);
/* Init: no FLASHes known */
for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
flash_info[i].flash_id = FLASH_UNKNOWN;
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
/* check whether the address is 0 */
if (flash_addr_table[index][i] == 0) {
continue;
}
/* call flash_get_size() to initialize sector address */
size_b[i] = flash_get_size((vu_long *)
flash_addr_table[index][i],
&flash_info[i]);
flash_info[i].size = size_b[i];
if (flash_info[i].flash_id == FLASH_UNKNOWN) {
printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
i, size_b[i], size_b[i] << 20);
flash_info[i].sector_count = -1;
flash_info[i].size = 0;
}
/* Monitor protection ON by default */
(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
&flash_info[2]);
#ifdef CFG_ENV_IS_IN_FLASH
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR,
CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1,
&flash_info[2]);
(void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND,
CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1,
&flash_info[2]);
#endif
total_b += flash_info[i].size;
}
return total_b;
}
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