Initial revision

board/netvia/config.mk

+#
+# (C) Copyright 2000
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+#
+# netVia Boards
+#
+
+TEXT_BASE = 0x40000000

board/netvia/flash.c

+/*
+ * (C) Copyright 2000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mpc8xx.h>
+
+flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+
+/*-----------------------------------------------------------------------
+ * Functions
+ */
+static ulong flash_get_size(vu_long * addr, flash_info_t * info);
+static int write_byte(flash_info_t * info, ulong dest, uchar data);
+static void flash_get_offsets(ulong base, flash_info_t * info);
+
+/*-----------------------------------------------------------------------
+ */
+
+unsigned long flash_init(void)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile memctl8xx_t *memctl = &immap->im_memctl;
+	unsigned long size;
+	int i;
+
+	/* Init: no FLASHes known */
+	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+		flash_info[i].flash_id = FLASH_UNKNOWN;
+	}
+
+	/* Static FLASH Bank configuration here - FIXME XXX */
+
+	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
+
+	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
+		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", size, size << 20);
+	}
+
+	/* Remap FLASH according to real size */
+	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+
+	/* Re-do sizing to get full correct info */
+	size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+
+	flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+
+	/* monitor protection ON by default */
+	flash_protect(FLAG_PROTECT_SET, CFG_FLASH_BASE, CFG_FLASH_BASE + CFG_MONITOR_LEN - 1, &flash_info[0]);
+
+	flash_info[0].size = size;
+
+	return (size);
+}
+
+/*-----------------------------------------------------------------------
+ */
+static void flash_get_offsets(ulong base, flash_info_t * info)
+{
+	int i;
+
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+}
+
+/*-----------------------------------------------------------------------
+ */
+void flash_print_info(flash_info_t * info)
+{
+	int i;
+
+	if (info->flash_id == FLASH_UNKNOWN) {
+		printf("missing or unknown FLASH type\n");
+		return;
+	}
+
+	switch (info->flash_id & FLASH_VENDMASK) {
+	case FLASH_MAN_AMD:
+		printf("AMD ");
+		break;
+	case FLASH_MAN_FUJ:
+		printf("FUJITSU ");
+		break;
+	case FLASH_MAN_MX:
+		printf("MXIC ");
+		break;
+	default:
+		printf("Unknown Vendor ");
+		break;
+	}
+
+	switch (info->flash_id & FLASH_TYPEMASK) {
+	case FLASH_AM040:
+		printf("AM29LV040B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400B:
+		printf("AM29LV400B (4 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM400T:
+		printf("AM29LV400T (4 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM800B:
+		printf("AM29LV800B (8 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM800T:
+		printf("AM29LV800T (8 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM160B:
+		printf("AM29LV160B (16 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM160T:
+		printf("AM29LV160T (16 Mbit, top boot sector)\n");
+		break;
+	case FLASH_AM320B:
+		printf("AM29LV320B (32 Mbit, bottom boot sect)\n");
+		break;
+	case FLASH_AM320T:
+		printf("AM29LV320T (32 Mbit, top boot sector)\n");
+		break;
+	default:
+		printf("Unknown Chip Type\n");
+		break;
+	}
+
+	printf("  Size: %ld MB in %d Sectors\n", info->size >> 20, info->sector_count);
+
+	printf("  Sector Start Addresses:");
+	for (i = 0; i < info->sector_count; ++i) {
+		if ((i % 5) == 0)
+			printf("\n   ");
+		printf(" %08lX%s", info->start[i], info->protect[i] ? " (RO)" : "     ");
+	}
+	printf("\n");
+}
+
+/*-----------------------------------------------------------------------
+ */
+
+
+/*-----------------------------------------------------------------------
+ */
+
+/*
+ * The following code cannot be run from FLASH!
+ */
+
+static ulong flash_get_size(vu_long * addr, flash_info_t * info)
+{
+	short i;
+	uchar mid;
+	uchar pid;
+	vu_char *caddr = (vu_char *) addr;
+	ulong base = (ulong) addr;
+
+
+	/* Write auto select command: read Manufacturer ID */
+	caddr[0x0555] = 0xAA;
+	caddr[0x02AA] = 0x55;
+	caddr[0x0555] = 0x90;
+
+	mid = caddr[0];
+	switch (mid) {
+	case (AMD_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_AMD;
+		break;
+	case (FUJ_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_FUJ;
+		break;
+	case (MX_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_MX;
+		break;
+	case (STM_MANUFACT & 0xFF):
+		info->flash_id = FLASH_MAN_STM;
+		break;
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		info->sector_count = 0;
+		info->size = 0;
+		return (0);				/* no or unknown flash  */
+	}
+
+	pid = caddr[1];				/* device ID        */
+	switch (pid) {
+	case (AMD_ID_LV400T & 0xFF):
+		info->flash_id += FLASH_AM400T;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV400B & 0xFF):
+		info->flash_id += FLASH_AM400B;
+		info->sector_count = 11;
+		info->size = 0x00080000;
+		break;					/* => 512 kB        */
+
+	case (AMD_ID_LV800T & 0xFF):
+		info->flash_id += FLASH_AM800T;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV800B & 0xFF):
+		info->flash_id += FLASH_AM800B;
+		info->sector_count = 19;
+		info->size = 0x00100000;
+		break;					/* => 1 MB      */
+
+	case (AMD_ID_LV160T & 0xFF):
+		info->flash_id += FLASH_AM160T;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV160B & 0xFF):
+		info->flash_id += FLASH_AM160B;
+		info->sector_count = 35;
+		info->size = 0x00200000;
+		break;					/* => 2 MB      */
+
+	case (AMD_ID_LV040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+	case (STM_ID_M29W040B & 0xFF):
+		info->flash_id += FLASH_AM040;
+		info->sector_count = 8;
+		info->size = 0x00080000;
+		break;
+
+#if 0							/* enable when device IDs are available */
+	case (AMD_ID_LV320T & 0xFF):
+		info->flash_id += FLASH_AM320T;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+
+	case (AMD_ID_LV320B & 0xFF):
+		info->flash_id += FLASH_AM320B;
+		info->sector_count = 67;
+		info->size = 0x00400000;
+		break;					/* => 4 MB      */
+#endif
+	default:
+		info->flash_id = FLASH_UNKNOWN;
+		return (0);				/* => no or unknown flash */
+
+	}
+
+	printf(" ");
+	/* set up sector start address table */
+	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) {
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000);
+		}
+	} else if (info->flash_id & FLASH_BTYPE) {
+		/* set sector offsets for bottom boot block type    */
+		info->start[0] = base + 0x00000000;
+		info->start[1] = base + 0x00004000;
+		info->start[2] = base + 0x00006000;
+		info->start[3] = base + 0x00008000;
+		for (i = 4; i < info->sector_count; i++) {
+			info->start[i] = base + (i * 0x00010000) - 0x00030000;
+		}
+	} else {
+		/* set sector offsets for top boot block type       */
+		i = info->sector_count - 1;
+		info->start[i--] = base + info->size - 0x00004000;
+		info->start[i--] = base + info->size - 0x00006000;
+		info->start[i--] = base + info->size - 0x00008000;
+		for (; i >= 0; i--) {
+			info->start[i] = base + i * 0x00010000;
+		}
+	}
+
+	/* check for protected sectors */
+	for (i = 0; i < info->sector_count; i++) {
+		/* read sector protection: D0 = 1 if protected */
+		caddr = (volatile unsigned char *)(info->start[i]);
+		info->protect[i] = caddr[2] & 1;
+	}
+
+	/*
+	 * Prevent writes to uninitialized FLASH.
+	 */
+	if (info->flash_id != FLASH_UNKNOWN) {
+		caddr = (vu_char *) info->start[0];
+
+		caddr[0x0555] = 0xAA;
+		caddr[0x02AA] = 0x55;
+		caddr[0x0555] = 0xF0;
+
+		udelay(20000);
+	}
+
+	return (info->size);
+}
+
+
+/*-----------------------------------------------------------------------
+ */
+
+int flash_erase(flash_info_t * info, int s_first, int s_last)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	int flag, prot, sect, l_sect;
+	ulong start, now, last;
+
+	if ((s_first < 0) || (s_first > s_last)) {
+		if (info->flash_id == FLASH_UNKNOWN) {
+			printf("- missing\n");
+		} else {
+			printf("- no sectors to erase\n");
+		}
+		return 1;
+	}
+
+	if ((info->flash_id == FLASH_UNKNOWN) ||
+	    (info->flash_id > FLASH_AMD_COMP)) {
+		printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
+		return 1;
+	}
+
+	prot = 0;
+	for (sect = s_first; sect <= s_last; ++sect) {
+		if (info->protect[sect]) {
+			prot++;
+		}
+	}
+
+	if (prot) {
+		printf("- Warning: %d protected sectors will not be erased!\n", prot);
+	} else {
+		printf("\n");
+	}
+
+	l_sect = -1;
+
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0x80;
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+
+	/* Start erase on unprotected sectors */
+	for (sect = s_first; sect <= s_last; sect++) {
+		if (info->protect[sect] == 0) {	/* not protected */
+			addr = (vu_char *) (info->start[sect]);
+			addr[0] = 0x30;
+			l_sect = sect;
+		}
+	}
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* wait at least 80us - let's wait 1 ms */
+	udelay(1000);
+
+	/*
+	 * We wait for the last triggered sector
+	 */
+	if (l_sect < 0)
+		goto DONE;
+
+	start = get_timer(0);
+	last = start;
+	addr = (vu_char *) (info->start[l_sect]);
+	while ((addr[0] & 0x80) != 0x80) {
+		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			printf("Timeout\n");
+			return 1;
+		}
+		/* show that we're waiting */
+		if ((now - last) > 1000) {	/* every second */
+			putc('.');
+			last = now;
+		}
+	}
+
+  DONE:
+	/* reset to read mode */
+	addr = (vu_char *) info->start[0];
+	addr[0] = 0xF0;				/* reset bank */
+
+	printf(" done\n");
+	return 0;
+}
+
+/*-----------------------------------------------------------------------
+ * Copy memory to flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+
+int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
+{
+	int rc;
+
+	while (cnt > 0) {
+		if ((rc = write_byte(info, addr++, *src++)) != 0) {
+			return (rc);
+		}
+		--cnt;
+	}
+
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ * Write a word to Flash, returns:
+ * 0 - OK
+ * 1 - write timeout
+ * 2 - Flash not erased
+ */
+static int write_byte(flash_info_t * info, ulong dest, uchar data)
+{
+	vu_char *addr = (vu_char *) (info->start[0]);
+	ulong start;
+	int flag;
+
+	/* Check if Flash is (sufficiently) erased */
+	if ((*((vu_char *) dest) & data) != data) {
+		return (2);
+	}
+	/* Disable interrupts which might cause a timeout here */
+	flag = disable_interrupts();
+
+	addr[0x0555] = 0xAA;
+	addr[0x02AA] = 0x55;
+	addr[0x0555] = 0xA0;
+
+	*((vu_char *) dest) = data;
+
+	/* re-enable interrupts if necessary */
+	if (flag)
+		enable_interrupts();
+
+	/* data polling for D7 */
+	start = get_timer(0);
+	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
+		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			return (1);
+		}
+	}
+	return (0);
+}
+
+/*-----------------------------------------------------------------------
+ */

cpu/mpc8xx/scc.c

+/*
+ * File:  scc.c
+ * Description:
+ * 	Basic ET HW initialization and packet RX/TX routines
+ *
+ * NOTE  <<<IMPORTANT:  PLEASE READ>>>:
+ *     Do not cache Rx/Tx buffers!
+ */
+
+/*
+ * MPC823 <-> MC68160 Connections:
+ *
+ * Setup MPC823 to work with MC68160 Enhanced Ethernet
+ * Serial Tranceiver as follows:
+ *
+ * MPC823 Signal                MC68160  Comments
+ * ------ ------                -------  --------
+ * PA-12 ETHTX    -------->   TX       Eth. Port Transmit Data
+ * PB-18 E_TENA   -------->   TENA     Eth. Transmit Port Enable
+ * PA-5 ETHTCK    <--------   TCLK     Eth. Port Transmit Clock
+ * PA-13 ETHRX    <--------   RX       Eth. Port Receive Data
+ * PC-8 E_RENA    <--------   RENA     Eth. Receive Enable
+ * PA-6 ETHRCK    <--------   RCLK     Eth. Port Receive Clock
+ * PC-9 E_CLSN    <--------   CLSN     Eth. Port Collision Indication
+ *
+ * FADS Board Signal              MC68160  Comments
+ * -----------------              -------  --------
+ * (BCSR1) ETHEN*     -------->  CS2      Eth. Port Enable
+ * (BSCR4) TPSQEL*    -------->  TPSQEL   Twisted Pair Signal Quality Error Test Enable
+ * (BCSR4) TPFLDL*    -------->  TPFLDL   Twisted Pair Full-Duplex
+ * (BCSR4) ETHLOOP    -------->  LOOP     Eth. Port Diagnostic Loop-Back
+ *
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <commproc.h>
+#include <net.h>
+#include <command.h>
+
+#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(SCC_ENET)
+
+/* Ethernet Transmit and Receive Buffers */
+#define DBUF_LENGTH  1520
+
+#define TX_BUF_CNT 2
+
+#define TOUT_LOOP 100
+
+static char txbuf[DBUF_LENGTH];
+
+static uint rxIdx;	/* index of the current RX buffer */
+static uint txIdx;	/* index of the current TX buffer */
+
+/*
+  * SCC Ethernet Tx and Rx buffer descriptors allocated at the
+  *  immr->udata_bd address on Dual-Port RAM
+  * Provide for Double Buffering
+  */
+
+typedef volatile struct CommonBufferDescriptor {
+    cbd_t rxbd[PKTBUFSRX];	/* Rx BD */
+    cbd_t txbd[TX_BUF_CNT];	/* Tx BD */
+} RTXBD;
+
+static RTXBD *rtx;
+
+static int scc_send(struct eth_device* dev, volatile void *packet, int length);
+static int scc_recv(struct eth_device* dev);
+static int scc_init (struct eth_device* dev, bd_t * bd);
+static void scc_halt(struct eth_device* dev);
+
+int scc_initialize(bd_t *bis)
+{
+	struct eth_device* dev;
+
+	dev = (struct eth_device*) malloc(sizeof *dev);
+
+	sprintf(dev->name, "SCC ETHERNET");
+	dev->iobase = 0;
+	dev->priv   = 0;
+	dev->init   = scc_init;
+	dev->halt   = scc_halt;
+	dev->send   = scc_send;
+	dev->recv   = scc_recv;
+
+	eth_register(dev);
+
+	return 1;
+}
+
+static int scc_send(struct eth_device* dev, volatile void *packet, int length)
+{
+	int i, j=0;
+#if 0
+	volatile char *in, *out;
+#endif
+
+	/* section 16.9.23.3
+	 * Wait for ready
+	 */
+#if 0
+	while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY);
+	out = (char *)(rtx->txbd[txIdx].cbd_bufaddr);
+	in = packet;
+	for(i = 0; i < length; i++) {
+		*out++ = *in++;
+	}
+	rtx->txbd[txIdx].cbd_datlen = length;
+	rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST);
+	while (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) j++;
+
+#ifdef ET_DEBUG
+	printf("cycles: %d    status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
+#endif
+	i = (rtx->txbd[txIdx++].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
+
+	/* wrap around buffer index when necessary */
+	if (txIdx >= TX_BUF_CNT) txIdx = 0;
+#endif
+
+	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
+		udelay (1);	/* will also trigger Wd if needed */
+		j++;
+	}
+	if (j>=TOUT_LOOP) printf("TX not ready\n");
+	rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
+	rtx->txbd[txIdx].cbd_datlen = length;
+	rtx->txbd[txIdx].cbd_sc |= (BD_ENET_TX_READY | BD_ENET_TX_LAST |BD_ENET_TX_WRAP);
+	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
+		udelay (1);	/* will also trigger Wd if needed */
+		j++;
+	}
+	if (j>=TOUT_LOOP) printf("TX timeout\n");
+#ifdef ET_DEBUG
+	printf("cycles: %d    status: %x\n", j, rtx->txbd[txIdx].cbd_sc);
+#endif
+	i = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS) /* return only status bits */;
+	return i;
+}
+
+static int scc_recv(struct eth_device* dev)
+{
+	int length;
+
+   for (;;) {
+	/* section 16.9.23.2 */
+	if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
+		length = -1;
+		break;     /* nothing received - leave for() loop */
+	}
+
+	length = rtx->rxbd[rxIdx].cbd_datlen;
+
+	if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
+#ifdef ET_DEBUG
+		printf("err: %x\n", rtx->rxbd[rxIdx].cbd_sc);
+#endif
+	} else {
+		/* Pass the packet up to the protocol layers. */
+		NetReceive(NetRxPackets[rxIdx], length - 4);
+	}
+
+
+	/* Give the buffer back to the SCC. */
+	rtx->rxbd[rxIdx].cbd_datlen = 0;
+
+	/* wrap around buffer index when necessary */
+	if ((rxIdx + 1) >= PKTBUFSRX) {
+           rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
+	   rxIdx = 0;
+	} else {
+           rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
+	   rxIdx++;
+	}
+   }
+   return length;
+}
+
+/**************************************************************
+  *
+  * SCC Ethernet Initialization Routine
+  *
+  *************************************************************/
+
+static int scc_init(struct eth_device* dev, bd_t *bis)
+{
+
+    int i;
+    scc_enet_t *pram_ptr;
+
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+
+#if defined(CONFIG_FADS)
+#if defined(CONFIG_MPC860T)
+    /* The FADS860T doesn't use the MODEM_EN or DATA_VOICE signals.	*/
+    *((uint *) BCSR4) &= ~BCSR4_ETHLOOP;
+    *((uint *) BCSR4) |= BCSR4_TFPLDL|BCSR4_TPSQEL;
+    *((uint *) BCSR1) &= ~BCSR1_ETHEN;
+#else
+    *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP|BCSR4_MODEM_EN);
+    *((uint *) BCSR4) |= BCSR4_TFPLDL|BCSR4_TPSQEL|BCSR4_DATA_VOICE;
+    *((uint *) BCSR1) &= ~BCSR1_ETHEN;
+#endif
+#endif
+
+    pram_ptr = (scc_enet_t *)&(immr->im_cpm.cp_dparam[PROFF_ENET]);
+
+    rxIdx = 0;
+    txIdx = 0;
+
+#ifdef CFG_ALLOC_DPRAM
+    rtx = (RTXBD *) (immr->im_cpm.cp_dpmem +
+    		     dpram_alloc_align(sizeof(RTXBD), 8));
+#else
+    rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE);
+#endif	/* 0 */
+
+#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD))
+    /* Configure port A pins for Txd and Rxd.
+    */
+    immr->im_ioport.iop_papar |=  (PA_ENET_RXD | PA_ENET_TXD);
+    immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD);
+    immr->im_ioport.iop_paodr &=                ~PA_ENET_TXD;
+#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD))
+    /* Configure port B pins for Txd and Rxd.
+    */
+    immr->im_cpm.cp_pbpar |=  (PB_ENET_RXD | PB_ENET_TXD);
+    immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD);
+    immr->im_cpm.cp_pbodr &=                ~PB_ENET_TXD;
+#else
+#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined
+#endif
+
+#if defined(PC_ENET_LBK)
+    /* Configure port C pins to disable External Loopback
+     */
+    immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK;
+    immr->im_ioport.iop_pcdir |=  PC_ENET_LBK;
+    immr->im_ioport.iop_pcso  &= ~PC_ENET_LBK;
+    immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */
+#endif	/* PC_ENET_LBK */
+
+    /* Configure port C pins to enable CLSN and RENA.
+    */
+    immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA);
+    immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA);
+    immr->im_ioport.iop_pcso  |=  (PC_ENET_CLSN | PC_ENET_RENA);
+
+    /* Configure port A for TCLK and RCLK.
+    */
+    immr->im_ioport.iop_papar |=  (PA_ENET_TCLK | PA_ENET_RCLK);
+    immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK);
+
+    /*
+     * Configure Serial Interface clock routing -- see section 16.7.5.3
+     * First, clear all SCC bits to zero, then set the ones we want.
+     */
+
+    immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK;
+    immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT;
+
+
+    /*
+     * Initialize SDCR -- see section 16.9.23.7
+     * SDMA configuration register
+     */
+    immr->im_siu_conf.sc_sdcr = 0x01;
+
+
+    /*
+     * Setup SCC Ethernet Parameter RAM
+     */
+
+    pram_ptr->sen_genscc.scc_rfcr = 0x18;  /* Normal Operation and Mot byte ordering */
+    pram_ptr->sen_genscc.scc_tfcr = 0x18;  /* Mot byte ordering, Normal access */
+
+    pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH;	/* max. ET package len 1520 */
+
+    pram_ptr->sen_genscc.scc_rbase = (unsigned int)(&rtx->rxbd[0]);      /* Set RXBD tbl start at Dual Port */
+    pram_ptr->sen_genscc.scc_tbase = (unsigned int)(&rtx->txbd[0]);      /* Set TXBD tbl start at Dual Port */
+
+    /*
+     * Setup Receiver Buffer Descriptors (13.14.24.18)
+     * Settings:
+     *     Empty, Wrap
+     */
+
+    for (i = 0; i < PKTBUFSRX; i++)
+    {
+      rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
+      rtx->rxbd[i].cbd_datlen = 0;                                 /* Reset */
+      rtx->rxbd[i].cbd_bufaddr = (uint)NetRxPackets[i];
+    }
+
+    rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
+
+    /*
+     * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19)
+     * Settings:
+     *    Add PADs to Short FRAMES, Wrap, Last, Tx CRC
+     */
+
+    for (i = 0; i < TX_BUF_CNT; i++)
+    {
+      rtx->txbd[i].cbd_sc = (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC);
+      rtx->txbd[i].cbd_datlen = 0;                                 /* Reset */
+      rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
+    }
+
+    rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
+
+    /*
+     * Enter Command:  Initialize Rx Params for SCC
+     */
+
+    do {				/* Spin until ready to issue command	*/
+	__asm__ ("eieio");
+    } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+    /* Issue command */
+    immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_RX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
+    do {				/* Spin until command processed		*/
+	__asm__ ("eieio");
+    } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+
+    /*
+     * Ethernet Specific Parameter RAM
+     *     see table 13-16, pg. 660,
+     *     pg. 681 (example with suggested settings)
+     */
+
+    pram_ptr->sen_cpres  = ~(0x0);	/* Preset CRC */
+    pram_ptr->sen_cmask  = 0xdebb20e3;	/* Constant Mask for CRC */
+    pram_ptr->sen_crcec  = 0x0;		/* Error Counter CRC (unused) */
+    pram_ptr->sen_alec   = 0x0;		/* Alignment Error Counter (unused) */
+    pram_ptr->sen_disfc  = 0x0;		/* Discard Frame Counter (unused) */
+    pram_ptr->sen_pads   = 0x8888;	/* Short Frame PAD Characters */
+
+    pram_ptr->sen_retlim = 15;		/* Retry Limit Threshold */
+    pram_ptr->sen_maxflr = 1518;	/* MAX Frame Length Register */
+    pram_ptr->sen_minflr = 64;		/* MIN Frame Length Register */
+
+    pram_ptr->sen_maxd1  = DBUF_LENGTH;	/* MAX DMA1 Length Register */
+    pram_ptr->sen_maxd2  = DBUF_LENGTH;	/* MAX DMA2 Length Register */
+
+    pram_ptr->sen_gaddr1 = 0x0;		/* Group Address Filter 1 (unused) */
+    pram_ptr->sen_gaddr2 = 0x0;		/* Group Address Filter 2 (unused) */
+    pram_ptr->sen_gaddr3 = 0x0;		/* Group Address Filter 3 (unused) */
+    pram_ptr->sen_gaddr4 = 0x0;		/* Group Address Filter 4 (unused) */
+
+#define ea eth_get_dev()->enetaddr
+    pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4];
+    pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2];
+    pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0];
+#undef ea
+
+    pram_ptr->sen_pper   = 0x0;		/* Persistence (unused) */
+    pram_ptr->sen_iaddr1 = 0x0;		/* Individual Address Filter 1 (unused) */
+    pram_ptr->sen_iaddr2 = 0x0;		/* Individual Address Filter 2 (unused) */
+    pram_ptr->sen_iaddr3 = 0x0;		/* Individual Address Filter 3 (unused) */
+    pram_ptr->sen_iaddr4 = 0x0;		/* Individual Address Filter 4 (unused) */
+    pram_ptr->sen_taddrh = 0x0;		/* Tmp Address (MSB) (unused) */
+    pram_ptr->sen_taddrm = 0x0;		/* Tmp Address (unused) */
+    pram_ptr->sen_taddrl = 0x0;		/* Tmp Address (LSB) (unused) */
+
+    /*
+     * Enter Command:  Initialize Tx Params for SCC
+     */
+
+    do {				/* Spin until ready to issue command	*/
+	__asm__ ("eieio");
+    } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+    /* Issue command */
+    immr->im_cpm.cp_cpcr = ((CPM_CR_INIT_TX << 8) | (CPM_CR_ENET << 4) | CPM_CR_FLG);
+    do {				/* Spin until command processed		*/
+	__asm__ ("eieio");
+    } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG);
+
+    /*
+     * Mask all Events in SCCM - we use polling mode
+     */
+    immr->im_cpm.cp_scc[SCC_ENET].scc_sccm = 0;
+
+    /*
+     * Clear Events in SCCE -- Clear bits by writing 1's
+     */
+
+    immr->im_cpm.cp_scc[SCC_ENET].scc_scce = ~(0x0);
+
+
+    /*
+     * Initialize GSMR High 32-Bits
+     * Settings:  Normal Mode
+     */
+
+    immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrh = 0;
+
+    /*
+     * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive
+     * Settings:
+     *     TCI = Invert
+     *     TPL =  48 bits
+     *     TPP = Repeating 10's
+     *     MODE = Ethernet
+     */
+
+    immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl = (	SCC_GSMRL_TCI	 |	\
+    						SCC_GSMRL_TPL_48 |	\
+						SCC_GSMRL_TPP_10 |	\
+						SCC_GSMRL_MODE_ENET);
+
+    /*
+     * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4
+     */
+
+    immr->im_cpm.cp_scc[SCC_ENET].scc_dsr = 0xd555;
+
+    /*
+     * Initialize the PSMR
+     * Settings:
+     *	CRC = 32-Bit CCITT
+     *	NIB = Begin searching for SFD 22 bits after RENA
+     *	FDE = Full Duplex Enable
+     *	LPB = Loopback Enable (Needed when FDE is set)
+     *	BRO = Reject broadcast packets
+     *	PROMISCOUS = Catch all packets regardless of dest. MAC adress
+     */
+    immr->im_cpm.cp_scc[SCC_ENET].scc_psmr  =	SCC_PSMR_ENCRC	|
+						SCC_PSMR_NIB22	|
+#if defined(CONFIG_SCC_ENET_FULL_DUPLEX)
+						SCC_PSMR_FDE	|
+						SCC_PSMR_LPB	|
+#endif
+#if defined(CONFIG_SCC_ENET_NO_BROADCAST)
+						SCC_PSMR_BRO	|
+#endif
+#if defined(CONFIG_SCC_ENET_PROMISCOUS)
+						SCC_PSMR_PRO	|
+#endif
+						0;
+
+    /*
+     * Configure Ethernet TENA Signal
+     */
+
+#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA))
+    immr->im_ioport.iop_pcpar |=  PC_ENET_TENA;
+    immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA;
+#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA))
+    immr->im_cpm.cp_pbpar |= PB_ENET_TENA;
+    immr->im_cpm.cp_pbdir |= PB_ENET_TENA;
+#else
+#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined
+#endif
+
+#if defined(CONFIG_ADS) && defined(CONFIG_MPC860)
+    /*
+     * Port C is used to control the PHY,MC68160.
+     */
+    immr->im_ioport.iop_pcdir |=
+	(PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL);
+
+    immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL;
+    immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL);
+    *((uint *) BCSR1) &= ~BCSR1_ETHEN;
+#endif	/* MPC860ADS */
+
+#if defined(CONFIG_AMX860)
+    /*
+     * Port B is used to control the PHY,MC68160.
+     */
+    immr->im_cpm.cp_pbdir |=
+        (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL);
+
+    immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL;
+    immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL);
+
+    immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN;
+    immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN;
+#endif  /* AMX860 */
+
+#ifdef CONFIG_RPXCLASSIC
+    *((uchar *)BCSR0) &= ~BCSR0_ETHLPBK;
+    *((uchar *)BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX);
+#endif
+
+#ifdef CONFIG_RPXLITE
+    *((uchar *)BCSR0) |= BCSR0_ETHEN ;
+#endif
+
+#ifdef CONFIG_MBX
+    board_ether_init();
+#endif
+
+#if defined(CONFIG_NETVIA)
+#if defined(PB_ENET_PDN)
+    immr->im_cpm.cp_pbpar &= ~PB_ENET_PDN;
+    immr->im_cpm.cp_pbdir |=  PB_ENET_PDN;
+    immr->im_cpm.cp_pbdat |=  PB_ENET_PDN;
+#elif defined(PC_ENET_PDN)
+    immr->im_cpm.cp_pcpar &= ~PC_ENET_PDN;
+    immr->im_cpm.cp_pcdir |=  PC_ENET_PDN;
+    immr->im_cpm.cp_pcdat |=  PC_ENET_PDN;
+#endif
+#endif
+
+    /*
+     * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive
+     */
+
+    immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+
+    /*
+     * Work around transmit problem with first eth packet
+     */
+#if defined (CONFIG_FADS)
+    udelay(10000);	/* wait 10 ms */
+#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC)
+    udelay(100000);	/* wait 100 ms */
+#endif
+
+    return 1;
+}
+
+
+
+static void scc_halt(struct eth_device* dev)
+{
+    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+}
+
+#if 0
+void restart(void)
+{
+   volatile immap_t *immr = (immap_t *)CFG_IMMR;
+   immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT);
+}
+#endif
+
+#endif	/* CFG_CMD_NET, SCC_ENET */

include/flash.h

+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _FLASH_H_
+#define _FLASH_H_
+
+#ifndef CFG_NO_FLASH
+/*-----------------------------------------------------------------------
+ * FLASH Info: contains chip specific data, per FLASH bank
+ */
+
+typedef struct {
+	ulong	size;			/* total bank size in bytes		*/
+	ushort	sector_count;		/* number of erase units		*/
+	ulong	flash_id;		/* combined device & manufacturer code	*/
+	ulong	start[CFG_MAX_FLASH_SECT];   /* physical sector start addresses	*/
+	uchar	protect[CFG_MAX_FLASH_SECT]; /* sector protection status	*/
+#ifdef CFG_FLASH_CFI
+	uchar	portwidth;		/* the width of the port		*/
+	uchar	chipwidth;		/* the width of the chip		*/
+	ushort  buffer_size;		/* # of bytes in write buffer		*/
+	ulong	erase_blk_tout;		/* maximum block erase timeout		*/
+	ulong	write_tout;		/* maximum write timeout		*/
+	ulong   buffer_write_tout;	/* maximum buffer write timeout		*/
+
+#endif
+} flash_info_t;
+
+/*
+ * Values for the width of the port
+ */
+#define FLASH_CFI_8BIT		0x01
+#define FLASH_CFI_16BIT		0x02
+#define FLASH_CFI_32BIT		0x04
+#define FLASH_CFI_64BIT		0x08
+/*
+ * Values for the width of the chip
+ */
+#define FLASH_CFI_BY8		0x01
+#define FLASH_CFI_BY16		0x02
+#define FLASH_CFI_BY32		0x04
+#define FLASH_CFI_BY64		0x08
+
+/* Prototypes */
+
+extern unsigned long flash_init (void);
+extern void flash_print_info (flash_info_t *);
+extern int flash_erase	(flash_info_t *, int, int);
+extern int flash_sect_erase (ulong addr_first, ulong addr_last);
+extern int flash_sect_protect (int flag, ulong addr_first, ulong addr_last);
+
+/* common/flash.c */
+extern void flash_protect (int flag, ulong from, ulong to, flash_info_t *info);
+extern int flash_write (uchar *, ulong, ulong);
+extern flash_info_t *addr2info (ulong);
+extern int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt);
+
+/* board/?/flash.c */
+#if defined(CFG_FLASH_PROTECTION)
+extern int flash_real_protect(flash_info_t *info, long sector, int prot);
+#endif	/* CFG_FLASH_PROTECTION */
+
+/*-----------------------------------------------------------------------
+ * return codes from flash_write():
+ */
+#define ERR_OK				0
+#define ERR_TIMOUT			1
+#define ERR_NOT_ERASED			2
+#define ERR_PROTECTED			4
+#define ERR_INVAL			8
+#define ERR_ALIGN			16
+#define ERR_UNKNOWN_FLASH_VENDOR	32
+#define ERR_UNKNOWN_FLASH_TYPE		64
+#define ERR_PROG_ERROR			128
+
+/*-----------------------------------------------------------------------
+ * Protection Flags for flash_protect():
+ */
+#define FLAG_PROTECT_SET	0x01
+#define FLAG_PROTECT_CLEAR	0x02
+
+/*-----------------------------------------------------------------------
+ * Device IDs
+ */
+
+#define AMD_MANUFACT	0x00010001	/* AMD     manuf. ID in D23..D16, D7..D0 */
+#define FUJ_MANUFACT	0x00040004	/* FUJITSU manuf. ID in D23..D16, D7..D0 */
+#define STM_MANUFACT	0x00200020	/* STM (Thomson) manuf. ID in D23.. -"-	*/
+#define SST_MANUFACT	0x00BF00BF	/* SST     manuf. ID in D23..D16, D7..D0 */
+#define MT_MANUFACT	0x00890089	/* MT      manuf. ID in D23..D16, D7..D0 */
+#define INTEL_MANUFACT	0x00890089	/* INTEL   manuf. ID in D23..D16, D7..D0 */
+#define	INTEL_ALT_MANU	0x00B000B0	/* alternate INTEL namufacturer ID	*/
+#define MX_MANUFACT	0x00C200C2	/* MXIC	   manuf. ID in D23..D16, D7..D0 */
+
+					/* Micron Technologies (INTEL compat.)	*/
+#define MT_ID_28F400_T	0x44704470	/* 28F400B3 ID ( 4 M, top boot sector)	*/
+#define MT_ID_28F400_B	0x44714471	/* 28F400B3 ID ( 4 M, bottom boot sect)	*/
+
+#define AMD_ID_LV040B	0x4F		/* 29LV040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+
+#define AMD_ID_F040B	0xA4		/* 29F040B ID				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define STM_ID_M29W040B	0xE3		/* M29W040B ID 				*/
+					/* 4 Mbit, 512K x 8,			*/
+					/* 8 64K x 8 uniform sectors		*/
+#define AMD_ID_F080B	0xD5		/* 29F080  ID  ( 1 M)			*/
+#define AMD_ID_F016D	0xAD		/* 29F016  ID  ( 2 M x 8)		*/
+#define AMD_ID_F032B	0x41		/* 29F032  ID  ( 4 M x 8)		*/
+#define AMD_ID_LV116DT	0xC7		/* 29LV116DT   ( 2 M x 8, top boot sect) */
+
+#define AMD_ID_LV400T	0x22B922B9	/* 29LV400T ID ( 4 M, top boot sector)	*/
+#define AMD_ID_LV400B	0x22BA22BA	/* 29LV400B ID ( 4 M, bottom boot sect)	*/
+
+#define AMD_ID_LV033C	0xA3		/* 29LV033C ID ( 4M x 8 )		*/
+
+#define AMD_ID_LV800T	0x22DA22DA	/* 29LV800T ID ( 8 M, top boot sector)	*/
+#define AMD_ID_LV800B	0x225B225B	/* 29LV800B ID ( 8 M, bottom boot sect)	*/
+
+#define AMD_ID_LV160T	0x22C422C4	/* 29LV160T ID (16 M, top boot sector)	*/
+#define AMD_ID_LV160B	0x22492249	/* 29LV160B ID (16 M, bottom boot sect)	*/
+
+#define AMD_ID_LV320T	0x22F622F6	/* 29LV320T ID (32 M, top boot sector)	*/
+#define AMD_ID_LV320B	0x22F922F9	/* 29LV320B ID (32 M, bottom boot sect)	*/
+
+#define AMD_ID_DL322T	0x22552255	/* 29DL322T ID (32 M, top boot sector)	*/
+#define AMD_ID_DL322B	0x22562256	/* 29DL322B ID (32 M, bottom boot sect)	*/
+#define AMD_ID_DL323T	0x22502250	/* 29DL323T ID (32 M, top boot sector)	*/
+#define AMD_ID_DL323B	0x22532253	/* 29DL323B ID (32 M, bottom boot sect)	*/
+#define AMD_ID_DL324T	0x225C225C	/* 29DL324T ID (32 M, top boot sector)	*/
+#define AMD_ID_DL324B	0x225F225F	/* 29DL324B ID (32 M, bottom boot sect) */
+
+#define AMD_ID_DL640	0x227E227E	/* 29DL640D ID (64 M, dual boot sectors)*/
+#define AMD_ID_LV640U	0x22D722D7	/* 29LV640U ID (64 M, uniform sectors)	*/
+
+#define SST_ID_xF200A	0x27892789	/* 39xF200A ID ( 2M = 128K x 16	)	*/
+#define SST_ID_xF400A	0x27802780	/* 39xF400A ID ( 4M = 256K x 16	)	*/
+#define SST_ID_xF800A	0x27812781	/* 39xF800A ID ( 8M = 512K x 16	)	*/
+#define SST_ID_xF160A	0x27822782	/* 39xF800A ID (16M =   1M x 16 )	*/
+
+#define STM_ID_F040B	0xE2		/* M29F040B ID ( 4M = 512K x 8  )	*/
+					/* 8 64K x 8 uniform sectors		*/
+
+#define STM_ID_x800AB	0x005B005B	/* M29W800AB ID (8M = 512K x 16	)	*/
+#define STM_ID_29W320DT	0x22CA22CA	/* M29W320DT ID (32 M, top boot sector)	*/
+#define STM_ID_29W320DB	0x22CB22CB	/* M29W320DB ID (32 M, bottom boot sect)	*/
+#define STM_ID_29W040B	0x00E300E3	/* M29W040B ID (4M = 512K x 8)	*/
+
+#define INTEL_ID_28F016S    0x66a066a0	/* 28F016S[VS] ID (16M = 512k x 16)	*/
+#define INTEL_ID_28F800B3T  0x88928892	/*  8M = 512K x 16 top boot sector	*/
+#define INTEL_ID_28F800B3B  0x88938893	/*  8M = 512K x 16 bottom boot sector	*/
+#define INTEL_ID_28F160B3T  0x88908890	/*  16M = 1M x 16 top boot sector	*/
+#define INTEL_ID_28F160B3B  0x88918891	/*  16M = 1M x 16 bottom boot sector	*/
+#define INTEL_ID_28F320B3T  0x88968896	/*  32M = 2M x 16 top boot sector	*/
+#define INTEL_ID_28F320B3B  0x88978897	/*  32M = 2M x 16 bottom boot sector	*/
+#define INTEL_ID_28F640B3T  0x88988898	/*  64M = 4M x 16 top boot sector	*/
+#define INTEL_ID_28F640B3B  0x88998899	/*  64M = 4M x 16 bottom boot sector	*/
+#define INTEL_ID_28F160F3B  0x88F488F4	/*  16M = 1M x 16 bottom boot sector	*/
+
+#define INTEL_ID_28F800C3T  0x88C088C0	/*  8M = 512K x 16 top boot sector	*/
+#define INTEL_ID_28F800C3B  0x88C188C1	/*  8M = 512K x 16 bottom boot sector	*/
+#define INTEL_ID_28F160C3T  0x88C288C2	/*  16M = 1M x 16 top boot sector	*/
+#define INTEL_ID_28F160C3B  0x88C388C3	/*  16M = 1M x 16 bottom boot sector	*/
+#define INTEL_ID_28F320C3T  0x88C488C4	/*  32M = 2M x 16 top boot sector	*/
+#define INTEL_ID_28F320C3B  0x88C588C5	/*  32M = 2M x 16 bottom boot sector	*/
+#define INTEL_ID_28F640C3T  0x88CC88CC	/*  64M = 4M x 16 top boot sector	*/
+#define INTEL_ID_28F640C3B  0x88CD88CD	/*  64M = 4M x 16 bottom boot sector	*/
+
+#define INTEL_ID_28F128J3   0x89189818  /*  16M = 8M x 16 x 128	*/
+#define INTEL_ID_28F640J5   0x00150015	/*  64M = 128K x  64			*/
+#define INTEL_ID_28F320J3A  0x00160016	/*  32M = 128K x  32			*/
+#define INTEL_ID_28F640J3A  0x00170017	/*  64M = 128K x  64			*/
+#define INTEL_ID_28F128J3A  0x00180018	/* 128M = 128K x 128			*/
+
+#define INTEL_ID_28F160S3   0x00D000D0	/*  16M = 512K x  32 (64kB x 32)	*/
+#define INTEL_ID_28F320S3   0x00D400D4	/*  32M = 512K x  64 (64kB x 64)	*/
+
+/* Note that the Sharp 28F016SC is compatible with the Intel E28F016SC */
+#define SHARP_ID_28F016SCL  0xAAAAAAAA	/* LH28F016SCT-L95 2Mx8, 32 64k blocks	*/
+#define SHARP_ID_28F016SCZ  0xA0A0A0A0	/* LH28F016SCT-Z4  2Mx8, 32 64k blocks	*/
+#define SHARP_ID_28F008SC   0xA6A6A6A6	/* LH28F008SCT-L12 1Mx8, 16 64k blocks	*/
+					/* LH28F008SCR-L85 1Mx8, 16 64k blocks	*/
+
+/*-----------------------------------------------------------------------
+ * Internal FLASH identification codes
+ *
+ * Be careful when adding new type! Odd numbers are "bottom boot sector" types!
+ */
+
+#define FLASH_AM040	0x0001		/* AMD Am29F040B, Am29LV040B
+					 * Bright Micro BM29F040
+					 * Fujitsu MBM29F040A
+					 * STM M29W040B
+					 * SGS Thomson M29F040B
+					 * 8 64K x 8 uniform sectors
+					 */
+#define FLASH_AM400T	0x0002		/* AMD AM29LV400			*/
+#define FLASH_AM400B	0x0003
+#define FLASH_AM800T	0x0004		/* AMD AM29LV800			*/
+#define FLASH_AM800B	0x0005
+#define FLASH_AM116DT	0x0026		/* AMD AM29LV116DT (2Mx8bit) */
+#define FLASH_AM160T	0x0006		/* AMD AM29LV160			*/
+#define FLASH_AM160LV	0x0046		/* AMD29LV160DB (2M = 2Mx8bit )	*/
+#define FLASH_AM160B	0x0007
+#define FLASH_AM320T	0x0008		/* AMD AM29LV320			*/
+#define FLASH_AM320B	0x0009
+
+#define FLASH_AMDL322T	0x0010		/* AMD AM29DL322			*/
+#define FLASH_AMDL322B	0x0011
+#define FLASH_AMDL323T	0x0012		/* AMD AM29DL323			*/
+#define FLASH_AMDL323B	0x0013
+#define FLASH_AMDL324T	0x0014		/* AMD AM29DL324			*/
+#define FLASH_AMDL324B	0x0015
+
+#define FLASH_AMDL640	0x0016		/* AMD AM29DL640D			*/
+#define FLASH_AMD016	0x0018		/* AMD AM29F016D			*/
+
+#define FLASH_SST200A	0x0040		/* SST 39xF200A ID (  2M = 128K x 16 )	*/
+#define FLASH_SST400A	0x0042		/* SST 39xF400A ID (  4M = 256K x 16 )	*/
+#define FLASH_SST800A	0x0044		/* SST 39xF800A ID (  8M = 512K x 16 )	*/
+#define FLASH_SST160A	0x0046		/* SST 39xF160A ID ( 16M =   1M x 16 )	*/
+
+#define FLASH_STM800AB	0x0051		/* STM M29WF800AB  (  8M = 512K x 16 )	*/
+#define FLASH_STMW320DT	0x0052		/* STM M29W320DT   (32 M, top boot sector)	*/
+#define FLASH_STMW320DB	0x0053		/* STM M29W320DB   (32 M, bottom boot sect)*/
+#define FLASH_STM320DB	0x00CB		/* STM M29W320DB (4M = 64K x 64, bottom)*/
+#define FLASH_STM800DT	0x00D7		/* STM M29W800DT (1M = 64K x 16, top)	*/
+#define FLASH_STM800DB	0x005B		/* STM M29W800DB (1M = 64K x 16, bottom)*/
+
+#define FLASH_28F400_T	0x0062		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
+#define FLASH_28F400_B	0x0063		/* MT  28F400B3 ID (  4M = 256K x 16 )	*/
+
+#define FLASH_INTEL800T 0x0074		/* INTEL 28F800B3T (  8M = 512K x 16 )	*/
+#define FLASH_INTEL800B 0x0075		/* INTEL 28F800B3B (  8M = 512K x 16 )	*/
+#define FLASH_INTEL160T 0x0076		/* INTEL 28F160B3T ( 16M =  1 M x 16 )	*/
+#define FLASH_INTEL160B 0x0077		/* INTEL 28F160B3B ( 16M =  1 M x 16 )	*/
+#define FLASH_INTEL320T 0x0078		/* INTEL 28F320B3T ( 32M =  2 M x 16 )	*/
+#define FLASH_INTEL320B 0x0079		/* INTEL 28F320B3B ( 32M =  2 M x 16 )	*/
+#define FLASH_INTEL640T 0x007A		/* INTEL 28F320B3T ( 64M =  4 M x 16 )	*/
+#define FLASH_INTEL640B 0x007B		/* INTEL 28F320B3B ( 64M =  4 M x 16 )	*/
+
+#define FLASH_28F320J3A 0x007C		/* INTEL 28F320J3A ( 32M = 128K x  32)	*/
+#define FLASH_28F640J3A 0x007D		/* INTEL 28F640J3A ( 64M = 128K x  64)	*/
+#define FLASH_28F128J3A 0x007E		/* INTEL 28F128J3A (128M = 128K x 128)	*/
+
+#define FLASH_28F008S5	0x0080		/* Intel 28F008S5  (  1M =  64K x 16 )	*/
+#define FLASH_28F016SV	0x0081		/* Intel 28F016SV  ( 16M = 512k x 32 )	*/
+#define FLASH_28F800_B	0x0083		/* Intel E28F800B  (  1M = ? )		*/
+#define FLASH_AM29F800B	0x0084		/* AMD Am29F800BB  (  1M = ? )		*/
+#define FLASH_28F320J5	0x0085		/* Intel 28F320J5  (  4M = 128K x 32 )	*/
+#define FLASH_28F160S3	0x0086		/* Intel 28F160S3  ( 16M = 512K x 32 )	*/
+#define FLASH_28F320S3	0x0088		/* Intel 28F320S3  ( 32M = 512K x 64 )	*/
+#define FLASH_AM640U	0x0090		/* AMD Am29LV640U  ( 64M = 4M x 16 )	*/
+#define FLASH_AM033C	0x0091		/* AMD AM29LV033   ( 32M = 4M x 8 )	*/
+#define FLASH_LH28F016SCT 0x0092	/* Sharp 28F016SCT ( 8 Meg Flash SIMM )	*/
+#define FLASH_28F160F3B	0x0093		/* Intel 28F160F3B ( 16M = 1M x 16 )	*/
+
+#define FLASH_28F640J5  0x0099		/* INTEL 28F640J5  ( 64M = 128K x  64)	*/
+
+#define FLASH_28F800C3T	0x009A		/* Intel 28F800C3T (  8M = 512K x 16 )	*/
+#define FLASH_28F800C3B	0x009B		/* Intel 28F800C3B (  8M = 512K x 16 )	*/
+#define FLASH_28F160C3T	0x009C		/* Intel 28F160C3T ( 16M = 1M x 16 )	*/
+#define FLASH_28F160C3B	0x009D		/* Intel 28F160C3B ( 16M = 1M x 16 )	*/
+#define FLASH_28F320C3T	0x009E		/* Intel 28F320C3T ( 32M = 2M x 16 )	*/
+#define FLASH_28F320C3B	0x009F		/* Intel 28F320C3B ( 32M = 2M x 16 )	*/
+#define FLASH_28F640C3T	0x00A0		/* Intel 28F640C3T ( 64M = 4M x 16 )	*/
+#define FLASH_28F640C3B	0x00A1		/* Intel 28F640C3B ( 64M = 4M x 16 )	*/
+
+#define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
+
+
+/* manufacturer offsets
+ */
+#define FLASH_MAN_AMD	0x00000000	/* AMD					*/
+#define FLASH_MAN_FUJ	0x00010000	/* Fujitsu				*/
+#define FLASH_MAN_BM	0x00020000	/* Bright Microelectronics		*/
+#define FLASH_MAN_MX	0x00030000	/* MXIC					*/
+#define FLASH_MAN_STM	0x00040000
+#define FLASH_MAN_SST	0x00100000
+#define FLASH_MAN_INTEL	0x00300000
+#define FLASH_MAN_MT	0x00400000
+#define FLASH_MAN_SHARP	0x00500000
+
+
+#define FLASH_TYPEMASK	0x0000FFFF	/* extract FLASH type   information	*/
+#define FLASH_VENDMASK	0xFFFF0000	/* extract FLASH vendor information	*/
+
+#define FLASH_AMD_COMP	0x000FFFFF	/* Up to this ID, FLASH is compatible	*/
+					/* with AMD, Fujitsu and SST		*/
+					/* (JEDEC standard commands ?)		*/
+
+#define FLASH_BTYPE	0x0001		/* mask for bottom boot sector type	*/
+
+/*-----------------------------------------------------------------------
+ * Timeout constants:
+ *
+ * We can't find any specifications for maximum chip erase times,
+ * so these values are guestimates.
+ */
+#define FLASH_ERASE_TIMEOUT	120000	/* timeout for erasing in ms		*/
+#define FLASH_WRITE_TIMEOUT	500	/* timeout for writes  in ms		*/
+
+#endif /* !CFG_NO_FLASH */
+
+#endif /* _FLASH_H_ */