- 20 Dec, 2020 2 commits
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Heinrich Schuchardt authored
tools/efivar.py allows to prepare a file with UEFI variables to preseed the UEFI variable store. Signed-off-by:Heinrich Schuchardt <xypron.glpk@gmx.de>
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Heinrich Schuchardt authored
Provide a description of the bootefi command. Signed-off-by:Heinrich Schuchardt <xypron.glpk@gmx.de>
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- 18 Dec, 2020 1 commit
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Pengpeng Chen authored
Add SPI Flash controller driver for Cortina Access CAxxxx SoCs Signed-off-by:
Pengpeng Chen <pengpeng.chen@cortina-access.com> Signed-off-by:
Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Vignesh R <vigneshr@ti.com> CC: Tom Rini <trini@konsulko.com> [jagan: rebase on master] Signed-off-by:
Jagan Teki <jagan@amarulasolutions.com> Reviewed-by:
Jagan Teki <jagan@amarulasolutions.com>
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- 09 Dec, 2020 1 commit
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Patrice Chotard authored
Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by:
Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by:
Patrick Delaunay <patrick.delaunay@st.com>
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- 02 Dec, 2020 1 commit
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Heinrich Schuchardt authored
include/log.h belongs to LOGGING. Signed-off-by:
Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by:
Simon Glass <sjg@chromium.org>
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- 30 Oct, 2020 1 commit
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Sean Anderson authored
Some commands can get very unweildy if they have too many positional arguments. Adding options makes them easier to read, remember, and understand. This implementation of getopt has been taken from barebox, which has had option support for quite a while. I have made a few modifications to their version, such as the removal of opterr in favor of a separate getopt_silent function. In addition, I have moved all global variables into struct getopt_context. The getopt from barebox also re-orders the arguments passed to it so that non-options are placed last. This allows users to specify options anywhere. For example, `ls -l foo/ -R` would be re-ordered to `ls -l -R foo/` as getopt parsed the options. However, this feature conflicts with the const argv in cmd_tbl->cmd. This was originally added in 54841ab5 ("Make sure that argv[] argument pointers are not modified."). The reason stated in that commit is that hush requires argv to stay unmodified. Has this situation changed? Barebox also uses hush, and does not have this problem. Perhaps we could use their fix? I have assigned maintenance of getopt to Simon Glass, as it is currently only used by the log command. I would also be fine maintaining it. Signed-off-by:
Sean Anderson <seanga2@gmail.com>
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- 29 Oct, 2020 1 commit
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Andre Przywara authored
Maxime mentioned that he feels not having the time to be an Allwinner maintainer anymore. Take over from him. Maxime, many thanks for your great work in the past! I hope I can still relay the occasional technical question to you in the future. Acked-by:
Maxime Ripard <mripard@kernel.org> Signed-off-by:
Andre Przywara <andre.przywara@arm.com>
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- 27 Oct, 2020 2 commits
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Heinrich Schuchardt authored
On a board without hardware clock this software real time clock can be used. The build time is used to initialize the RTC. So you will have to adjust the time either manually using the 'date' command or use the 'sntp' to update the RTC with the time from a network time server. See CONFIG_CMD_SNTP and CONFIG_BOOTP_NTPSERVER. The RTC time is advanced according to CPU ticks. Signed-off-by:Heinrich Schuchardt <xypron.glpk@gmx.de>
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Michal Simek authored
Add fragment to cover documenation for Xilinx platforms. Signed-off-by:
Michal Simek <michal.simek@xilinx.com> Reviewed-by:
Heinrich Schuchardt <xypron.glpk@gmx.de>
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- 26 Oct, 2020 2 commits
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Sean Anderson authored
Half of this driver is a DM-based timer driver, and half is RISC-V-specific IPI code. Move the timer portions in with the other timer drivers. The KConfig is not moved, since it also enables IPIs. It could also be split into two configs, but no boards use the timer but not the IPI atm, so I haven't split it. Signed-off-by:
Sean Anderson <seanga2@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Rick Chen <rick@andestech.com>
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Sean Anderson authored
This is a regular timer driver, and should live with the other timer drivers. Signed-off-by:
Sean Anderson <seanga2@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Rick Chen <rick@andestech.com>
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- 22 Oct, 2020 3 commits
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Robert Marko authored
Add support for the hardware pseudo random number generator found in Qualcomm SoC-s. Signed-off-by:Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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Robert Marko authored
This adds the driver for the IPQ40xx built-in MDIO. This will be needed to support future PHY driver. Signed-off-by:Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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Robert Marko authored
This patch adds support for the Qualcomm QUP SPI controller that is commonly found in most of Qualcomm SoC-s. Driver currently supports v1.1.1, v2.1.1 and v2.2.1 HW. FIFO and Block modes are supported, no support for DMA mode is planned. Signed-off-by:
Robert Marko <robert.marko@sartura.hr> Signed-off-by:
Luka Kovacic <luka.kovacic@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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- 21 Oct, 2020 2 commits
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Patrick Delaunay authored
Add the STM32MP1 RNG driver in the list of drivers supported by the STMicroelectronics STM32MP15x series. Signed-off-by:
Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by:
Patrice Chotard <patrice.chotard@st.com>
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Patrick Delaunay authored
Add files and directories regex "stm32" and "stm" in "ARM STM STM32MP" platform to avoid missing files or drivers supported by the STMicroelectronics series STM32MP15x. This patch adds the rules already used in Linux kernel for ARM/STM32 ARCHITECTURE. Signed-off-by:
Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by:
Patrice Chotard <patrice.chotard@st.com>
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- 19 Oct, 2020 1 commit
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Chunfeng Yun authored
Add MediaTek USB3 Dual-Role controller driver to ARM MEDIATEK, and add myself as a maintainer for it. Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com>
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- 08 Oct, 2020 2 commits
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Sean Anderson authored
The Fully-Programmable Input/Output Array (FPIOA) device controls pin multiplexing on the K210. The FPIOA can remap any supported function to any multifunctional IO pin. It can also perform basic GPIO functions, such as reading the current value of a pin. However, GPIO functionality remains largely unimplemented (in favor of the dedicated GPIO peripherals). Signed-off-by:
Sean Anderson <seanga2@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Sean Anderson authored
This extends the pinctrl-sandbox driver to support pin muxing, and adds a test for that behaviour. The test is done in C and not python (like the existing tests for the pinctrl uclass) because it needs to call pinctrl_select_state. Another option could be to add a command that invokes pinctrl_select_state and then test everything in test/py/tests/test_pinmux.py. The pinctrl-sandbox driver now mimics the way that many pinmux devices work. There are two groups of pins which are muxed together, as well as four pins which are muxed individually. I have tried to test all normal paths. However, very few error cases are explicitly checked for. Signed-off-by:
Sean Anderson <seanga2@gmail.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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- 06 Oct, 2020 1 commit
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Heinrich Schuchardt authored
Add doc/arch/sandbox.rst to the scope of SANDBOX. Signed-off-by:
Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by:
Simon Glass <sjg@chromium.org>
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- 05 Oct, 2020 1 commit
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Claudiu Beznea authored
Add basic CPU driver use to retrieve information about CPU itself. Signed-off-by:Claudiu Beznea <claudiu.beznea@microchip.com>
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- 28 Sep, 2020 1 commit
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Claudiu Beznea authored
Add Microchip PIT64B timer. Signed-off-by:Claudiu Beznea <claudiu.beznea@microchip.com>
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- 18 Sep, 2020 2 commits
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Robert Marko authored
Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by:Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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Robert Marko authored
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets. So since this will be needed by further drivers, lets add a driver for the reset controller. Signed-off-by:Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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- 16 Sep, 2020 3 commits
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Miquel Raynal authored
I also followed the development of the SquashFS support in U-Boot as part of Joao Marcos internship, so I would also appreciate receiving new contributions and bug reports related to this topic. Signed-off-by:Miquel Raynal <miquel.raynal@bootlin.com>
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Thomas Petazzoni authored
As I have followed the development of the SquashFS support in U-Boot as part of Joao Marcos work, it makes sense to get Cc'ed on contributions/bug reports related to the squashfs support. Signed-off-by:Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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Baruch Siach authored
Signed-off-by:Baruch Siach <baruch@tkos.co.il>
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- 09 Sep, 2020 2 commits
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Robert Marko authored
Import Qualcomm IPQ4019 GCC bindings from Linux. This will enable using bindings instead of raw clock numbers both in the driver and DTS like Linux does. Signed-off-by:Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
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Rayagonda Kokatanur authored
Update MAINTAINERS file for new files. Signed-off-by:
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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- 08 Sep, 2020 1 commit
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Qu Wenruo authored
Since the current code base is mostly from btrfs-progs, anyone contributing to U-Boot btrfs code could also help us to improve btrfs-progs and btrfs kernel module. Also add myself as designated reviewer. Signed-off-by:
Qu Wenruo <wqu@suse.com> Reviewed-by:
Marek Behún <marek.behun@nic.cz>
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- 31 Aug, 2020 1 commit
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Masahiro Yamada authored
I am leaving Socionext. Orphan the UniPhier platform until somebody takes the role. Signed-off-by:Masahiro Yamada <yamada.masahiro@socionext.com>
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- 24 Aug, 2020 1 commit
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Anastasiia Lukianenko authored
Signed-off-by:
Anastasiia Lukianenko <anastasiia_lukianenko@epam.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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- 14 Aug, 2020 1 commit
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Chia-Wei, Wang authored
Update maintainers for Aspeed SoC platforms. Signed-off-by:Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
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- 08 Aug, 2020 4 commits
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Jway Lin authored
Add Cortina Access LED controller support for CAxxxx SOCs Signed-off-by:
Jway Lin <jway.lin@cortina-access.com> Signed-off-by:
Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Simon Glass <sjg@chromium.org> Add head file fixed link error and remove unused flashing function Reviewed-by:
Simon Glass <sjg@chromium.org>
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Joao Marcos Costa authored
Add Python scripts to test 'ls' and 'load' commands. The scripts generate a SquashFS image and clean the directory after the assertions, or if an exception is raised. Signed-off-by:Joao Marcos Costa <joaomarcos.costa@bootlin.com>
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Joao Marcos Costa authored
Add 'ls' and 'load' commands. Signed-off-by:Joao Marcos Costa <joaomarcos.costa@bootlin.com>
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Joao Marcos Costa authored
Add support for SquashFS filesystem. Right now, it does not support compression but support for zlib will be added in a follow-up commit. Signed-off-by:Joao Marcos Costa <joaomarcos.costa@bootlin.com>
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- 29 Jul, 2020 3 commits
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Rayagonda Kokatanur authored
Update MAINTAINERS for broadcom ns3 platform (TARGET_NS3). Signed-off-by:
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by:
Simon Glass <sjg@chromium.org>
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Stefan Bosch authored
Changes in relation to FriendlyARM's U-Boot nanopi2-v2016.01: - Configuration changed, mainly several "CONFIG_..." moved from s5p4418_nanopi2.h to s5p4418_nanopi2_defconfig and USB related configs removed because USB is not supported yet. - s5p4418_nanopi2.h: "CONFIG_" removed from several s5p4418/nanopi2 specific defines because the appropriate values do not need to be configurable. - pinctrl is supported now, therefore "CONFIG_PINCTRL=y" added to s5p4418_nanopi2_defconfig. Signed-off-by:Stefan Bosch <stefan_b@posteo.net>
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Robert Marko authored
This introduces initial support for the popular Qualcomm IPQ40x8 and IPQ40x9 WiSoC series. IPQ40xx series have 4x Cortex A7 ARM-v7A cores. Supported are: IPQ4018, IPQ4019, IPQ4028 and IPQ4029. IPQ40x8 and IPQ40x9 use the same cores, but differ in addressable RAM size (1GB for IPQ40x9 and 256MB for IPQ40x8) and supported peripherals (IPQ40x8 lacks RGMII, LCD controller and EMMC/SDHCI controllers). IQP4028/IPQ4029 models differ from IPQ4018/IPQ4019 only by their rated temperatures rates with IPQ402X models being rated for wider temperature ranges. Initially this supports: * Simple clock driver (Only for UART1 now, will be extended) * Pinctrl driver (Supports UARTX and GPIO now, will be extended) * GPIOs already supported by msm_gpio driver with updates * UARTs already supported by serial_msm driver with updates Further peripherals will come in later patches. Signed-off-by:Robert Marko <robert.marko@sartura.hr>
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