- 10 Dec, 2020 1 commit
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Meenakshi Aggarwal authored
LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by:
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com>
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- 23 Oct, 2020 1 commit
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Razvan Ionut Cirjan authored
As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by:
Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com>
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- 24 Sep, 2020 1 commit
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Meenakshi Aggarwal authored
Make sure that SW_RST_REQ and RST_REQ_MSK are cleared before triggering hardware reset request. Signed-off-by:
Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Signed-off-by:
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Reviewed-by:
Priyanka Jain <priyanka.jain@nxp.com>
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- 17 Jul, 2020 1 commit
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Masahiro Yamada authored
The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada ...
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- 19 May, 2020 2 commits
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Simon Glass authored
Move this uncommon header out of the common header. Signed-off-by:Simon Glass <sjg@chromium.org>
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Simon Glass authored
Move this header out of the common header. Signed-off-by:Simon Glass <sjg@chromium.org>
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- 18 May, 2020 1 commit
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Simon Glass authored
Move this header out of the common header. Network support is used in quite a few places but it still does not warrant blanket inclusion. Note that this net.h header itself has quite a lot in it. It could be split into the driver-mode support, functions, structures, checksumming, etc. Signed-off-by:Simon Glass <sjg@chromium.org>
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- 17 May, 2020 1 commit
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Michael Walle authored
Virtually all callers of this function do the rounding on their own. Some do it right, some don't. Instead of doing this in each caller, do the rounding in efi_add_memory_map(). Change the size parameter to bytes instead of pages and remove aligning and size calculation in all callers. There is no more need to make the original efi_add_memory_map() (which takes pages as size) available outside the module. Thus rename it to efi_add_memory_map_pg() and make it static to prevent further misuse outside the module. Signed-off-by:
Michael Walle <michael@walle.cc> Add missing comma in sunxi_display.c. Reviewed-by:
Heinrich Schuchardt <xypron.glpk@gmx.de>
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- 29 Apr, 2020 1 commit
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Madalin Bucur authored
Probe the FMan MACs based on the device tree while retaining the legacy code/functionality. One notable change introduced here is that, for DM_ETH, the name of the interfaces is corrected to the fmX-macY format, that avoids the referral to the MAC block names which were incorrect for FMan v3 devices (i.e. DTSEC, TGEC) and had weird formatting (i.e. FM1@DTSEC6, FM1@TGEC1). The legacy code is left unchanged in this respect. Signed-off-by:
Madalin Bucur <madalin.bucur@oss.nxp.com> Reviewed-by:
Priyanka Jain <priyanka.jain@nxp.com>
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- 28 Apr, 2020 1 commit
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Hou Zhiqiang authored
The initialization of gd->arch.resv_ram pointer should depend on if the RESV_RAM config is enabled. Signed-off-by:
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by:
Wasim Khan <wasim.khan@nxp.com> Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com>
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- 24 Jan, 2020 3 commits
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Simon Glass authored
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by:
Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by:
Tom Rini <trini@konsulko.com>
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Simon Glass authored
These functions relate to memory init so move them into the init header. Signed-off-by:Simon Glass <sjg@chromium.org>
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Alex Marginean authored
Exports the serdes configuration as an environment variable for LS gen 3 SoCs, so it can be used in u-boot command line. It should particularly be useful for applying Linux DT overlays for the given serdes configuration. This code is called from arch_misc_init and not from the existing serdes_init function because it depends on U-Boot environment being set up. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by:
Priyanka Jain <priyanka.jain@nxp.com>
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- 17 Jan, 2020 2 commits
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Simon Glass authored
At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by:
Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by:
Tom Rini <trini@konsulko.com>
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Simon Glass authored
These functions relate to memory init so move them into the init header. Signed-off-by:Simon Glass <sjg@chromium.org>
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- 26 Dec, 2019 1 commit
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Alex Marginean authored
Hardware comes out of reset with implicit values, but these are outside the accepted range for Layerscape gen 3 chassis spec used on LS1028A. Allocate different IDs and fix up Linux DT to use them. Signed-off-by:
Alex Marginean <alexandru.marginean@nxp.com> Reviewed-by:
Bin Meng <bmeng.cn@gmail.com> Tested-by:
Michael Walle <michael@walle.cc> Reviewed-by:
Priyanka Jain <priyanka.jain@nxp.com>
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- 02 Dec, 2019 3 commits
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Simon Glass authored
These functions belong in cpu_func.h since they do not use driver model. Move them over. Don't bother adding comments since these functions should be deleted. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Tom Rini <trini@konsulko.com>
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Simon Glass authored
This function belongs in mii.h so move it over. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Tom Rini <trini@konsulko.com>
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Simon Glass authored
At present this function sits in its own file but it does not really justify it. There are similar string functions in vsprintf.h, so move it there. Also add the missing function comment. Use the vsprintf.h include file explicitly where needed. Signed-off-by:
Simon Glass <sjg@chromium.org> Reviewed-by:
Tom Rini <trini@konsulko.com>
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- 08 Nov, 2019 2 commits
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Pankaj Bansal authored
While getting the 'subarg' of 'hwconfig' env variable in config_core_prefetch(), if no hwconfig variable is defined, below warning is received: WARNING: Calling __hwconfig without a buffer and before environment is ready Fix this by checking 'hwconfig' env variable. If not found return without further processing. Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com> Tested-by:
Michael Walle <michael@walle.cc>
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Mathew McBride authored
If the secure world reset handlers are used (via CONFIG_PSCI_RESET), then do not use the layerscape-specific implementation. Signed-off-by:
Mathew McBride <matt@traverse.com.au> Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com>
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- 21 Oct, 2019 1 commit
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Yuantian Tang authored
Add LS1027A, LS1018A and LS1017A personalities support to LS1028A SoC family. LS1028A is the prime personality of LS1028A SoC family. LS1027A is a lower funtionality version of QorIQ LS1028A which does not support the multimedia subsystems, such as LCD controller, GPU, and eDP PHY. The QorIQ LS1018A and LS1017A SoCs are single 64-bit Arm A72 core, low power versions of the QorIQ LS1028A and LS1027A SoCs respectively. Signed-off-by:
Tang Yuantian <andy.tang@nxp.com> Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com>
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- 12 Sep, 2019 1 commit
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Thomas Schaefer authored
The SP805-WDT module on LS1028A requires configuration of PMU's PCTBENR register to enable watchdog counter decrement and reset signal generation. The watchdog clock needs to be enabled first. Signed-off-by:
Thomas Schaefer <thomas.schaefer@kontron.com> Signed-off-by:
Zhao Qiang <qiang.zhao@nxp.com> Reviewed-by:
Priyanka Jain <priyanka.jain@nxp.com>
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- 11 Aug, 2019 2 commits
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Simon Glass authored
This file contains lots of internal details about the environment. Most code can include env.h instead, calling the functions there as needed. Rename this file and add a comment at the top to indicate its internal nature. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Joe Hershberger <joe.hershberger@ni.com> Reviewed-by:
Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> [trini: Fixup apalis-tk1.c] Signed-off-by:
Tom Rini <trini@konsulko.com>
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Simon Glass authored
Move this function over to the new header file. Signed-off-by:
Simon Glass <sjg@chromium.org> Acked-by:
Joe Hershberger <joe.hershberger@ni.com>
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- 22 May, 2019 4 commits
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Udit Agarwal authored
ENVL_NOWHERE is dependent on CONFIG_ENV_IS_NOWHERE and not on CONFIG_CHAIN_OF_TRUST so return ENVL_NOWHERE when CONFIG_ENV_IS_NOWHERE is enabled Signed-off-by:
Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Yuantian Tang authored
Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by:
Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by:
Rai Harninder <harninder.rai@nxp.com> Signed-off-by:
Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by:
Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by:
Tang Yuantian <andy.tang@nxp.com> Reviewed-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Hou Zhiqiang authored
The lx2160a have up to 6 PCIe controllers and have different address and size of PCIe region. Signed-off-by:
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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Hou Zhiqiang authored
Change to use PCIe address macro to determine if precompile the PCIe MMU table entry. Signed-off-by:
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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- 18 May, 2019 1 commit
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Trevor Woerner authored
While converting CONFIG_SYS_[DI]CACHE_OFF to Kconfig, there are instances where these configuration items are conditional on SPL. This commit adds SPL variants of these configuration items, uses CONFIG_IS_ENABLED(), and updates the configurations as required. Acked-by:
Alexey Brodkin <abrodkin@synopsys.com> Signed-off-by:
Trevor Woerner <trevor@toganlabs.com> [trini: Make the default depend on the setting for full U-Boot, update more zynq hardware] Signed-off-by:
Tom Rini <trini@konsulko.com>
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- 19 Feb, 2019 1 commit
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Pankaj Bansal authored
some dpmacs in armv8a based freescale layerscape SOCs can be configured via both serdes(sgmii, xfi, xlaui etc) bits and via EC*_PMUX(rgmii) bits in RCW. e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits Now if a dpmac is enabled by serdes bits then it takes precedence over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII, then the dpmac is SGMII and not RGMII. Therefore, move the fsl_rgmii_init after fsl_serdes_init. in fsl_rgmii_init function of SOC, we will check if the dpmac is enabled or not? if it is (fsl_serdes_init has already enabled the dpmac), then don't enable it. Signed-off-by:
Pankaj Bansal <pankaj.bansal@nxp.com> Reviewed-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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- 17 Jan, 2019 2 commits
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Hou Zhiqiang authored
LS1043A/LS1023A 23x23 package silicon has different SVR:VAR_PER. Signed-off-by:
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Rajesh Bhagat authored
Fixes for TFABOOT framework - update eMMC bootsrc to SD_MMC - Increase buffer size for mcinitcmd from 256 to 512 - Fix mcinitcmd and bootcmd for Secure Boot Signed-off-by:
Pankit Garg <pankit.garg@nxp.com> Signed-off-by:
Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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- 06 Dec, 2018 7 commits
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Priyanka Jain authored
LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by:
Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by:
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by:
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by:
Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by:
Sriram Dash <sriram.dash@nxp.com> Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Priyanka Jain authored
NXP layerscape architecture Chassis 3.2 builds upon chassis3 architecture with changes like DDR Memory map change, removal of IFC and support of upto 8 I2C controller. Patch add README.lsch3_2 and the above changes under macro CONFIG_NXP_LSCH3_2. Signed-off-by:
Sriram Dash <sriram.dash@nxp.com> Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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York Sun authored
Workaround of erratum A010539 clears the RCW source field in PORSR1 register, causing failure of detecting boot source using this method. Use SMC call if U-Boot runs at EL2. If SMC is not implemented or running at EL3, continue to read PORSR1 and presume QSPI as boot source if erratum workaround A010539 is enabled and RCW source is cleared. Signed-off-by:York Sun <york.sun@nxp.com>
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Rajesh Bhagat authored
Adds SMC calls for getting DDR size and bank info for TFABOOT. Signed-off-by:
Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by:
Pankit Garg <pankit.garg@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Pankit Garg authored
Adds bootcmd identificaton on basis on boot source, valid in TFABOOT configuration. Signed-off-by:
Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by:
Pankit Garg <pankit.garg@nxp.com> [YS: remove unnecessary braces] Reviewed-by:
York Sun <york.sun@nxp.com>
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Rajesh Bhagat authored
PORSR register holds the cfg_rcw_src field which can be used to identify boot source. Further, it can be used to select the environment location. Signed-off-by:
Pankit Garg <pankit.garg@nxp.com> Signed-off-by:
Rajesh Bhagat <rajesh.bhagat@nxp.com> [YS: fix multiple checkpatch issues] Reviewed-by:
York Sun <york.sun@nxp.com>
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Rajesh Bhagat authored
Adds TFABOOT support config option and add generic code to enable execution from DDR. Signed-off-by:
York Sun <york.sun@nxp.com> Signed-off-by:
Rajesh Bhagat <rajesh.bhagat@nxp.com>
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