- 10 Dec, 2020 1 commit
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Meenakshi Aggarwal authored
LX2162 is LX2160 based SoC, it has same die as of LX2160 with different packaging. LX2162A support 64-bit 2.9GT/s DDR4 memory, i2c, micro-click module, microSD card, eMMC support, serial console, qspi nor flash, qsgmii, sgmii, 25g, 40g, 50g network interface, one usb 3.0 and serdes interface to support three PCIe gen3 interface. Signed-off-by:
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> [Fixed whitespace errors] Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com>
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- 22 May, 2019 1 commit
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Yuantian Tang authored
Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by:
Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by:
Rai Harninder <harninder.rai@nxp.com> Signed-off-by:
Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by:
Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by:
Tang Yuantian <andy.tang@nxp.com> Reviewed-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
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- 06 Dec, 2018 1 commit
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Priyanka Jain authored
LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by:
Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by:
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by:
Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by:
Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by:
Sriram Dash <sriram.dash@nxp.com> Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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- 11 Sep, 2017 1 commit
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Ashish Kumar authored
LS1088A is compliant with the Layerscape Chassis Generation 3 with eight ARM v8 Cortex-A53 cores in 2 cluster, CCI-400, one 64-bit DDR4 SDRAM memory controller with ECC, Data path acceleration architecture 2.0 (DPAA2), Ethernet interfaces (SGMIIs, RGMIIs, QSGMIIs, XFIs), QSPI, IFC, PCIe, SATA, USB, SDXC, DUARTs etc. Signed-off-by:
Alison Wang <alison.wang@nxp.com> Signed-off-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Signed-off-by:
Ashish Kumar <Ashish.Kumar@nxp.com> Signed-off-by:
Raghav Dogra <raghav.dogra@nxp.com> Signed-off-by:
Shaohui Xie <Shaohui.Xie@nxp.com> [YS: Revised commit message] Reviewed-by:
York Sun <york.sun@nxp.com>
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- 23 May, 2017 1 commit
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Priyanka Jain authored
The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A72 cores and is built on layerscape architecture. It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A). So feature-wise it is same as LS2084A. LS2041A is a 4-core personality of LS2081A. Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by:
Santan Kumar <santan.kumar@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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- 22 Nov, 2016 1 commit
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Priyanka Jain authored
The QorIQ LS2088A SoC is built on layerscape architecture. It is similar to LS2080A SoC with some differences like 1)Timer controller offset is different 2)It has A72 cores 3)It supports TZASC module Signed-off-by:
Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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- 26 Jul, 2016 1 commit
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Mingkai Hu authored
The LS1046A processor is built on the QorIQ LS series architecture combining four ARM A72 processor cores with DPAA 1.0 support. Signed-off-by:
Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by:
Mihai Bantea <mihai.bantea@freescale.com> Signed-off-by:
Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by:
Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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- 03 Jun, 2016 2 commits
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Prabhakar Kushwaha authored
The QorIQ LS1012A processor, optimized for battery-backed or USB-powered, integrates a single ARM Cortex-A53 core with a hardware packet forwarding engine and high-speed interfaces to deliver line-rate networking performance. This patch add support of LS1012A SoC along with - Update platform & DDR clock read logic as per SVR - Define MMDC controller register set. - Update LUT base address for PCIe - Avoid L3 platform cache compilation - Update USB address, errata - SerDes table - Added CSU IDs for SDHC2, SAI-1 to SAI-4 Signed-off-by:
Calvin Johnson <calvin.johnson@nxp.com> Signed-off-by:
Makarand Pawagi <makarand.pawagi@mindspeed.com> Signed-off-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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Prabhakar Kushwaha authored
SoC overviews are getting repeated across board folders. So, Organize SoC overview at common location i.e. fsl-layerscape/doc Also move README.lsch2 and README.lsch3 in same folder. Signed-off-by:
Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by:
York Sun <york.sun@nxp.com>
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