arch/arm/dts/am335x-regor-rdk-u-boot.dtsi

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2020 Linumiz
+ */
+
+/ {
+	chosen {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		bootargs = "console=ttyO0,115200 earlyprintk";
+		stdout-path = &uart0;
+	};
+
+	ocp {
+		u-boot,dm-pre-reloc;
+	};
+};
+
+&i2c0 {
+	u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+	u-boot,dm-pre-reloc;
+};
+
+&mmc1 {
+	u-boot,dm-pre-reloc;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+};

arch/arm/dts/am335x-regor-rdk.dts

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ */
+
+/dts-v1/;
+
+#include "am335x-phycore-som.dtsi"
+#include "am335x-regor.dtsi"
+
+/* SoM */
+&gpmc {
+	status = "okay";
+};
+
+&i2c_eeprom {
+	status = "okay";
+};
+
+&serial_flash {
+	status = "okay";
+};

arch/arm/dts/am335x-regor.dtsi

+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 Phytec Messtechnik GmbH
+ * Author: Teresa Remmet <t.remmet@phytec.de>
+ *
+ */
+
+/ {
+	model = "Phytec AM335x phyBOARD-REGOR";
+	compatible = "phytec,am335x-regor", "phytec,am335x-phycore-som", "ti,am33xx";
+
+	vcc3v3: fixedregulator@1 {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-boot-on;
+	};
+
+	/* User IO */
+	user_leds: user_leds {
+		compatible = "gpio-leds";
+		pinctrl-names = "default";
+		pinctrl-0 = <&user_leds_pins>;
+
+		run_stop-led {
+			gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "gpio";
+			default-state = "off";
+		};
+
+		error-led {
+			gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>;
+			linux,default-trigger = "gpio";
+			default-state = "off";
+		};
+	};
+};
+
+/* User Leds */
+&am33xx_pinmux {
+	user_leds_pins: pinmux_user_leds {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x8E0, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* lcd_hsync.gpio2_22 */
+			AM33XX_IOPAD(0x994, PIN_OUTPUT_PULLDOWN | MUX_MODE7)	/* mcasp0_fsx.gpio3_15 */
+		>;
+	};
+};
+
+/* CAN Busses */
+&am33xx_pinmux {
+	dcan1_pins: pinmux_dcan1 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2)	/* uart0_ctsn.d_can1_tx */
+			AM33XX_IOPAD(0x96C, PIN_INPUT_PULLUP | MUX_MODE2)	/* uart0_rtsn.d_can1_rx */
+		>;
+	};
+};
+
+&dcan1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&dcan1_pins>;
+	status = "okay";
+};
+
+/* Ethernet */
+&am33xx_pinmux {
+	ethernet1_pins: pinmux_ethernet1 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a0.mii2_txen */
+			AM33XX_IOPAD(0x844, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a1.mii2_rxdv */
+			AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a2.mii2_txd3 */
+			AM33XX_IOPAD(0x84C, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a3.mii2_txd2 */
+			AM33XX_IOPAD(0x850, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a4.mii2_txd1 */
+			AM33XX_IOPAD(0x854, PIN_OUTPUT | MUX_MODE1)		/* gpmc_a5.mii2_txd0 */
+			AM33XX_IOPAD(0x858, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a6.mii2_txclk */
+			AM33XX_IOPAD(0x85C, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a7.mii2_rxclk */
+			AM33XX_IOPAD(0x860, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a8.mii2_rxd3 */
+			AM33XX_IOPAD(0x864, PIN_INPUT_PULLDOWN | MUX_MODE1)	 /* gpmc_a9.mii2_rxd2 */
+			AM33XX_IOPAD(0x868, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a10.mii2_rxd1 */
+			AM33XX_IOPAD(0x86C, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_a11.mii2_rxd0 */
+			AM33XX_IOPAD(0x874, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_wpn.mii2_rxerr */
+			AM33XX_IOPAD(0x878, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* gpmc_ben1.mii2_col */
+		>;
+	};
+};
+
+&cpsw_emac1 {
+	phy-handle = <&phy1>;
+	phy-mode = "mii";
+	dual_emac_res_vlan = <2>;
+};
+
+&davinci_mdio {
+	phy1: ethernet-phy@1 {
+		reg = <1>;
+	};
+};
+
+&mac {
+	slaves = <2>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&ethernet0_pins &ethernet1_pins>;
+	dual_emac = <1>;
+};
+
+/* GPIOs */
+&am33xx_pinmux {
+	pinctrl-names = "default";
+	pinctrl-0 = <&user_gpios_pins>;
+
+	user_gpios_pins: pinmux_user_gpios {
+		pinctrl-single,pins = <
+			/* DIGIN 1-4 */
+			AM33XX_IOPAD(0x82C, PIN_INPUT | MUX_MODE7)		/* gpmc_ad11.gpio0_27 */
+			AM33XX_IOPAD(0x828, PIN_INPUT | MUX_MODE7)		/* gpmc_ad10.gpio0_26 */
+			AM33XX_IOPAD(0x824, PIN_INPUT | MUX_MODE7)		/* gpmc_ad9.gpio0_23 */
+			AM33XX_IOPAD(0x820, PIN_INPUT | MUX_MODE7)		/* gpmc_ad8.gpio0_22 */
+			/* DIGOUT 1-4 */
+			AM33XX_IOPAD(0x83C, PIN_OUTPUT | MUX_MODE7)		/* gpmc_ad15.gpio1_15 */
+			AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE7)		/* gpmc_ad14.gpio1_14 */
+			AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE7)		/* gpmc_ad13.gpio1_13 */
+			AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE7)		/* gpmc_ad12.gpio1_12 */
+		>;
+	};
+};
+
+/* MMC */
+&am33xx_pinmux {
+	mmc1_pins: pinmux_mmc1 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x8F0, PIN_INPUT_PULLUP | MUX_MODE0)
+			AM33XX_IOPAD(0x8F4, PIN_INPUT_PULLUP | MUX_MODE0)
+			AM33XX_IOPAD(0x8F8, PIN_INPUT_PULLUP | MUX_MODE0)
+			AM33XX_IOPAD(0x8FC, PIN_INPUT_PULLUP | MUX_MODE0)
+			AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0)
+			AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0)
+			AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE7)	/* spi0_cs1.mmc0_sdcd */
+		>;
+	};
+};
+
+&mmc1 {
+	vmmc-supply = <&vcc3v3>;
+	bus-width = <4>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc1_pins>;
+	cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
+	status = "okay";
+};
+
+/* RTC */
+&i2c_rtc {
+	status = "okay";
+};
+
+/* UARTs */
+&am33xx_pinmux {
+	uart0_pins: pinmux_uart0 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0)
+			AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+		>;
+	};
+
+	uart2_pins: pinmux_uart2 {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x92C, PIN_INPUT_PULLUP | MUX_MODE1)	/* mii1_tx_clk.uart2_rxd */
+			AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1)	/* mii1_rx_clk.uart2_txd */
+		>;
+	};
+};
+
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_pins>;
+	status = "okay";
+};
+
+&uart2 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart2_pins>;
+	status = "okay";
+};
+
+/* RS485 - UART1 */
+&am33xx_pinmux {
+	uart1_rs485_pins: pinmux_uart1_rs485_pins {
+		pinctrl-single,pins = <
+			AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0)
+			AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0)
+			AM33XX_IOPAD(0x97C, PIN_OUTPUT_PULLUP | MUX_MODE0)
+		>;
+	};
+};
+
+&uart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_rs485_pins>;
+	status = "okay";
+	linux,rs485-enabled-at-boot-time;
+};

arch/arm/dts/armada-3720-espressobin-emmc.dts

-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Device Tree file for Globalscale Marvell ESPRESSOBin Board with eMMC
- * Copyright (C) 2018 Marvell
- *
- * Romain Perier <romain.perier@free-electrons.com>
- * Konstantin Porotchkin <kostap@marvell.com>
- *
- */
-/*
- * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
- */
-
-/dts-v1/;
-
-#include "armada-3720-espressobin.dtsi"
-
-/ {
-	model = "Globalscale Marvell ESPRESSOBin Board (eMMC)";
-	compatible = "globalscale,espressobin-emmc", "globalscale,espressobin",
-		     "marvell,armada3720", "marvell,armada3710";
-};
-
-/* U11 */
-&sdhci1 {
-	non-removable;
-	bus-width = <8>;
-	mmc-ddr-1_8v;
-	mmc-hs400-1_8v;
-	marvell,xenon-emmc;
-	marvell,xenon-tun-count = <9>;
-	marvell,pad-type = "fixed-1-8v";
-
-	pinctrl-names = "default";
-	pinctrl-0 = <&mmc_pins>;
-	status = "okay";
-
-	#address-cells = <1>;
-	#size-cells = <0>;
-	mmccard: mmccard@0 {
-		compatible = "mmc-card";
-		reg = <0>;
-	};
-};

arch/arm/dts/armada-3720-espressobin.dts

-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 /*
- * Device Tree file for Globalscale Marvell ESPRESSOBin Board
+ * Device Tree file for Marvell Armada 3720 community board
+ * (ESPRESSOBin)
  * Copyright (C) 2016 Marvell
  *
- * Romain Perier <romain.perier@free-electrons.com>
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Konstantin Porotchkin <kostap@marvell.com>
  *
- */
-/*
- * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This file is distributed in the hope that it will be useful
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
 /dts-v1/;
 
-#include "armada-3720-espressobin.dtsi"
+#include "armada-372x.dtsi"
 
 / {
 	model = "Globalscale Marvell ESPRESSOBin Board";
 	compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		ethernet0 = &eth0;
+		i2c0 = &i2c0;
+		spi0 = &spi0;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
+	};
+
+	vcc_sd_reg0: regulator@0 {
+		compatible = "regulator-gpio";
+		regulator-name = "vcc_sd0";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		regulator-type = "voltage";
+		states = <1800000 0x1
+			  3300000 0x0>;
+		gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
+	};
+};
+
+&comphy {
+	max-lanes = <3>;
+	phy0 {
+		phy-type = <PHY_TYPE_USB3_HOST0>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+
+	phy1 {
+		phy-type = <PHY_TYPE_PEX0>;
+		phy-speed = <PHY_SPEED_2_5G>;
+	};
+
+	phy2 {
+		phy-type = <PHY_TYPE_SATA0>;
+		phy-speed = <PHY_SPEED_5G>;
+	};
+};
+
+&eth0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
+	phy-mode = "rgmii";
+	phy_addr = <0x1>;
+	fixed-link {
+		speed = <1000>;
+		full-duplex;
+	};
+};
+
+&i2c0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins>;
+	status = "okay";
+};
+
+/* CON3 */
+&sata {
+	status = "okay";
+};
+
+&sdhci0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdio_pins>;
+	bus-width = <4>;
+	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
+	vqmmc-supply = <&vcc_sd_reg0>;
+	status = "okay";
+};
+
+/* U11 */
+&sdhci1 {
+	non-removable;
+	bus-width = <8>;
+	mmc-ddr-1_8v;
+	mmc-hs400-1_8v;
+	marvell,xenon-emmc;
+	marvell,xenon-tun-count = <9>;
+	marvell,pad-type = "fixed-1-8v";
+
+	pinctrl-names = "default";
+	pinctrl-0 = <&mmc_pins>;
+	status = "okay";
+
+	#address-cells = <1>;
+	#size-cells = <0>;
+	mmccard: mmccard@0 {
+		compatible = "mmc-card";
+		reg = <0>;
+	};
+};
+
+&spi0 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&spi_quad_pins>;
+
+	spi-flash@0 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "st,m25p128", "jedec,spi-nor";
+		reg = <0>; /* Chip select 0 */
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+	};
+};
+
+/* Exported on the micro USB connector CON32 through an FTDI */
+&uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart1_pins>;
+	status = "okay";
+};
+
+/* CON29 */
+&usb2 {
+	status = "okay";
+};
+
+/* CON31 */
+&usb3 {
+	status = "okay";
+};
+
+&pcie0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pcie_pins>;
+	reset-gpios = <&gpiosb 3 GPIO_ACTIVE_LOW>;
+	status = "okay";
 };

arch/arm/dts/armada-xp-gp-u-boot.dtsi

+// SPDX-License-Identifier: GPL-2.0+
+
+/ {
+	soc {
+		internal-regs {
+			serial@12000 {
+				u-boot,dm-pre-reloc;
+			};
+		};
+	};
+};
+
+&spi0 {
+	u-boot,dm-pre-reloc;
+
+	spi-flash@0 {
+		u-boot,dm-pre-reloc;
+	};
+};

arch/arm/dts/armada-xp-gp.dts

@@ -31,6 +31,10 @@
 		stdout-path = "serial0:115200n8";
 	};
 
+	aliases {
+		spi0 = &spi0;
+	};
+
 	memory@0 {
 		device_type = "memory";
 		/*

arch/arm/dts/armv7-m.dtsi

-#include "skeleton.dtsi"
-
+// SPDX-License-Identifier: GPL-2.0
 / {
 	nvic: interrupt-controller@e000e100  {
 		compatible = "arm,armv7m-nvic";
@@ -22,4 +21,3 @@
 		ranges;
 	};
 };
-

arch/arm/dts/at91-sama5d2_icp.dts

@@ -53,19 +53,19 @@
 				status = "okay";
 
 				eeprom@50 {
-					compatible = "atmel,24c32";
+					compatible = "microchip,24aa02e48";
 					reg = <0x50>;
 					pagesize = <16>;
 				};
 
 				eeprom@52 {
-					compatible = "atmel,24c32";
+					compatible = "microchip,24aa02e48";
 					reg = <0x52>;
 					pagesize = <16>;
 				};
 
 				eeprom@53 {
-					compatible = "atmel,24c32";
+					compatible = "microchip,24aa02e48";
 					reg = <0x53>;
 					pagesize = <16>;
 				};

arch/arm/dts/axp803.dtsi

-/*
- * Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- *  a) This file is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This file is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- *  b) Permission is hereby granted, free of charge, to any person
- *     obtaining a copy of this software and associated documentation
- *     files (the "Software"), to deal in the Software without
- *     restriction, including without limitation the rights to use,
- *     copy, modify, merge, publish, distribute, sublicense, and/or
- *     sell copies of the Software, and to permit persons to whom the
- *     Software is furnished to do so, subject to the following
- *     conditions:
- *
- *     The above copyright notice and this permission notice shall be
- *     included in all copies or substantial portions of the Software.
- *
- *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- *     OTHER DEALINGS IN THE SOFTWARE.
- */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+// Copyright 2017 Icenowy Zheng <icenowy@aosc.xyz>
 
 /*
  * AXP803 Integrated Power Management Chip
@@ -49,6 +10,39 @@
 	interrupt-controller;
 	#interrupt-cells = <1>;
 
+	ac_power_supply: ac-power-supply {
+		compatible = "x-powers,axp803-ac-power-supply",
+			     "x-powers,axp813-ac-power-supply";
+		status = "disabled";
+	};
+
+	axp_adc: adc {
+		compatible = "x-powers,axp803-adc", "x-powers,axp813-adc";
+		#io-channel-cells = <1>;
+	};
+
+	axp_gpio: gpio {
+		compatible = "x-powers,axp803-gpio", "x-powers,axp813-gpio";
+		gpio-controller;
+		#gpio-cells = <2>;
+
+		gpio0_ldo: gpio0-ldo {
+			pins = "GPIO0";
+			function = "ldo";
+		};
+
+		gpio1_ldo: gpio1-ldo {
+			pins = "GPIO1";
+			function = "ldo";
+		};
+	};
+
+	battery_power_supply: battery-power-supply {
+		compatible = "x-powers,axp803-battery-power-supply",
+			     "x-powers,axp813-battery-power-supply";
+		status = "disabled";
+	};
+
 	regulators {
 		/* Default work frequency for buck regulators */
 		x-powers,dcdc-freq = <3000>;
@@ -152,4 +146,10 @@
 			status = "disabled";
 		};
 	};
+
+	usb_power_supply: usb-power-supply {
+		compatible = "x-powers,axp803-usb-power-supply",
+			     "x-powers,axp813-usb-power-supply";
+		status = "disabled";
+	};
 };

arch/arm/dts/fsl-imx8qm-mek-u-boot.dtsi

@@ -118,8 +118,11 @@
 
 &usdhc1 {
 	u-boot,dm-spl;
+	mmc-hs400-1_8v;
 };
 
 &usdhc2 {
 	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
 };

arch/arm/dts/fsl-imx8qxp-apalis-u-boot.dtsi

+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2020 Toradex
+ */
+
+&{/imx8qx-pm} {
+
+	u-boot,dm-pre-proper;
+};
+
+&mu {
+	u-boot,dm-pre-proper;
+};
+
+&clk {
+	u-boot,dm-pre-proper;
+};
+
+&iomuxc {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio0 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio1 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio2 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio3 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio4 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio5 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio6 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_lsio_gpio7 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_dma {
+	u-boot,dm-pre-proper;
+};
+
+&pd_dma_lpuart0 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_dma_lpuart3 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_conn {
+	u-boot,dm-pre-proper;
+};
+
+&pd_conn_sdch0 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_conn_sdch1 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_conn_sdch2 {
+	u-boot,dm-pre-proper;
+};
+
+&pd_conn_enet0 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio0 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio1 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio2 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio3 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio4 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio5 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio6 {
+	u-boot,dm-pre-proper;
+};
+
+&gpio7 {
+	u-boot,dm-pre-proper;
+};
+
+&lpuart3 {
+	u-boot,dm-pre-proper;
+};
+
+&lpuart0 {
+	u-boot,dm-pre-proper;
+};
+
+&usdhc1 {
+	u-boot,dm-pre-proper;
+	/delete-property/ assigned-clock-parents;
+};
+
+&usdhc2 {
+	u-boot,dm-pre-proper;
+	/delete-property/ assigned-clock-parents;
+};

arch/arm/dts/fsl-imx8qxp-apalis.dts

+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2020 Toradex
+ */
+
+/dts-v1/;
+
+#include "fsl-imx8qxp.dtsi"
+#include "fsl-imx8qxp-apalis-u-boot.dtsi"
+
+/ {
+	model = "Toradex Apalis iMX8X";
+	compatible = "toradex,apalis-imx8x", "fsl,imx8qxp";
+
+	chosen {
+		bootargs = "console=ttyLP1,115200";
+		stdout-path = &lpuart1;
+	};
+
+	regulators {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		reg_usb_otg1_vbus: regulator@0 {
+			compatible = "regulator-fixed";
+			reg = <0>;
+			regulator-name = "usb_otg1_vbus";
+			regulator-min-microvolt = <5000000>;
+			regulator-max-microvolt = <5000000>;
+			gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>;
+			enable-active-high;
+		};
+	};
+};
+
+&iomuxc {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_hog0>, <&pinctrl_hog1>, <&pinctrl_reset_moci>;
+
+	apalis-imx8x {
+		/* Apalis UART1 */
+		pinctrl_lpuart1: lpuart1grp {
+			fsl,pins = <
+				SC_P_UART1_RX_ADMA_UART1_RX		0x06000020	/* SODIMM 118 */
+				SC_P_UART1_TX_ADMA_UART1_TX		0x06000020	/* SODIMM 112 */
+			>;
+		};
+
+		/* On-module Gigabit Ethernet PHY Micrel KSZ9031 */
+		pinctrl_fec1: fec1grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD	0x14a0
+				SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD	0x14a0
+				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000020
+				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000020
+				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x61
+				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x61
+				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x61
+				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x61
+				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x61
+				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x61
+				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x61
+				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x61
+				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x61
+				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x61
+				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x61
+				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x61
+				/* On-module ETH_RESET# */
+				SC_P_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04		0x06000020
+				/* On-module ETH_INT# */
+				SC_P_ADC_IN2_LSIO_GPIO1_IO12			0x21
+			>;
+		};
+
+		/* Apalis BKL_ON */
+		pinctrl_gpio_bkl_on: gpio-bkl-on {
+			fsl,pins = <
+				SC_P_QSPI0A_DQS_LSIO_GPIO3_IO13			0x40		/* SODIMM 286 */
+			>;
+		};
+
+		pinctrl_hog0: hog0grp {
+			fsl,pins = <
+				SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD		0x000514a0
+			>;
+		};
+
+		pinctrl_hog1: hog1grp {
+			fsl,pins = <
+				/* Apalis USBO1_EN */
+				SC_P_QSPI0A_SCLK_LSIO_GPIO3_IO16		0x41		/* SODIMM 274 */
+			>;
+		};
+
+		/* Apalis RESET_MOCI# */
+		pinctrl_reset_moci: gpioresetmocigrp {
+			fsl,pins = <
+				SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01	0x21
+			>;
+		};
+
+		/* On-module eMMC */
+		pinctrl_usdhc1: usdhc1grp {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD			0x21
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21
+			>;
+		};
+
+		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD			0x21
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21
+			>;
+		};
+
+		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+			fsl,pins = <
+				SC_P_EMMC0_CLK_CONN_EMMC0_CLK			0x06000041
+				SC_P_EMMC0_CMD_CONN_EMMC0_CMD			0x21
+				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0		0x21
+				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1		0x21
+				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2		0x21
+				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3		0x21
+				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4		0x21
+				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5		0x21
+				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6		0x21
+				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7		0x21
+				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE		0x41
+				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B		0x21
+			>;
+		};
+
+		/* Apalis MMC1_CD# */
+		pinctrl_usdhc2_gpio: mmc1gpiogrp {
+			fsl,pins = <
+				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22		0x06000021	/* SODIMM 164 */
+			>;
+		};
+
+		pinctrl_usdhc2_gpio_sleep: usdhc1gpioslpgrp {
+			fsl,pins = <
+				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22		0x60		/* SODIMM 164 */
+			>;
+		};
+
+		/* Apalis USBH_EN */
+		pinctrl_usbh_en: usbhen {
+			fsl,pins = <
+				SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04		0x40		/* SODIMM 84 */
+			>;
+		};
+
+		/* Apalis MMC1 */
+		pinctrl_usdhc2: usdhc2grp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041	/* SODIMM 154 */
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD			0x21		/* SODIMM 150 */
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 160 */
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM 162 */
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM 144 */
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM 146 */
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21
+			>;
+		};
+
+		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041	/* SODIMM 154 */
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD			0x21		/* SODIMM 150 */
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 160 */
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM 162 */
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM 144 */
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM 146 */
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21
+			>;
+		};
+
+		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_CONN_USDHC1_CLK			0x06000041	/* SODIMM 154 */
+				SC_P_USDHC1_CMD_CONN_USDHC1_CMD			0x21		/* SODIMM 150 */
+				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0		0x21		/* SODIMM 160 */
+				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1		0x21		/* SODIMM 162 */
+				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2		0x21		/* SODIMM 144 */
+				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3		0x21		/* SODIMM 146 */
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21
+			>;
+		};
+
+		pinctrl_usdhc2_sleep: usdhc2slpgrp {
+			fsl,pins = <
+				SC_P_USDHC1_CLK_LSIO_GPIO4_IO23			0x60		/* SODIMM 154 */
+				SC_P_USDHC1_CMD_LSIO_GPIO4_IO24			0x60		/* SODIMM 150 */
+				SC_P_USDHC1_DATA0_LSIO_GPIO4_IO25		0x60		/* SODIMM 160 */
+				SC_P_USDHC1_DATA1_LSIO_GPIO4_IO26		0x60		/* SODIMM 162 */
+				SC_P_USDHC1_DATA2_LSIO_GPIO4_IO27		0x60		/* SODIMM 144 */
+				SC_P_USDHC1_DATA3_LSIO_GPIO4_IO28		0x60		/* SODIMM 146 */
+				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT		0x21
+			>;
+		};
+	};
+};
+
+/* Apalis Gigabit LAN */
+&fec1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_fec1>;
+	fsl,magic-packet;
+	phy-handle = <&ethphy0>;
+	phy-mode = "rgmii";
+	phy-reset-duration = <10>;
+	phy-reset-post-delay = <150>;
+	phy-reset-gpios = <&gpio3 4 GPIO_ACTIVE_LOW>;
+	status = "okay";
+
+	mdio {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		ethphy0: ethernet-phy@4 {
+			compatible = "ethernet-phy-ieee802.3-c22";
+			reg = <4>;
+		};
+	};
+};
+
+/* Apalis UART1 */
+&lpuart1 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_lpuart1>;
+	status = "okay";
+};
+
+/* On-module eMMC */
+&usdhc1 {
+	bus-width = <8>;
+	non-removable;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz";
+	pinctrl-0 = <&pinctrl_usdhc1>;
+	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+	status = "okay";
+};
+
+/* Apalis MMC1 */
+&usdhc2 {
+	bus-width = <4>;
+	cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
+	pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+	pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+	disable-wp;
+	status = "okay";
+};

arch/arm/dts/fsl-imx8qxp-mek-u-boot.dtsi

@@ -118,8 +118,11 @@
 
 &usdhc1 {
 	u-boot,dm-spl;
+	mmc-hs400-1_8v;
 };
 
 &usdhc2 {
 	u-boot,dm-spl;
+	sd-uhs-sdr104;
+	sd-uhs-ddr50;
 };

arch/arm/dts/fsl-ls1012a.dtsi

 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
+ * Copyright 2020 NXP
  * Copyright 2016 Freescale Semiconductor
  */
 
@@ -116,7 +117,7 @@
 			status = "disabled";
 		};
 
-		pcie@3400000 {
+		pcie1: pcie@3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03480000 0x0 0x40000   /* lut registers */

arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi

@@ -4,8 +4,8 @@
 
 / {
 	aliases {
-		mmc0 = &esdhc0;
-		mmc1 = &esdhc1;
+		mmc0 = &esdhc1;
+		mmc1 = &esdhc0;
 		i2c0 = &i2c0;
 		i2c1 = &i2c3;
 		i2c2 = &i2c4;

arch/arm/dts/fsl-ls1028a.dtsi

@@ -2,7 +2,7 @@
 /*
  * NXP ls1028a SOC common device tree source
  *
- * Copyright 2019 NXP
+ * Copyright 2019-2020 NXP
  *
  */
 
@@ -91,7 +91,7 @@
 		status = "disabled";
 	};
 
-	pcie@3400000 {
+	pcie1: pcie@3400000 {
 	       compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
 	       reg = <0x00 0x03400000 0x0 0x80000
 		       0x00 0x03480000 0x0 0x40000   /* lut registers */
@@ -107,7 +107,7 @@
 		       0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie@3500000 {
+	pcie2: pcie@3500000 {
 	       compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie";
 	       reg = <0x00 0x03500000 0x0 0x80000
 		       0x00 0x03580000 0x0 0x40000   /* lut registers */

arch/arm/dts/fsl-ls1043a.dtsi

 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Device Tree Include file for Freescale Layerscape-1043A family SoC.
+ * Device Tree Include file for NXP Layerscape-1043A family SoC.
  *
+ * Copyright 2020 NXP
  * Copyright (C) 2014-2015, Freescale Semiconductor
  *
  * Mingkai Hu <Mingkai.hu@freescale.com>
@@ -240,7 +241,7 @@
 			dr_mode = "host";
 		};
 
-		pcie@3400000 {
+		pcie1: pcie@3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
 			       0x00 0x03410000 0x0 0x10000   /* lut registers */
@@ -255,7 +256,7 @@
 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie@3500000 {
+		pcie2: pcie@3500000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
 			       0x00 0x03510000 0x0 0x10000   /* lut registers */
@@ -271,7 +272,7 @@
 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie@3600000 {
+		pcie3: pcie@3600000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
 			       0x00 0x03610000 0x0 0x10000   /* lut registers */

arch/arm/dts/fsl-ls1046a.dtsi

@@ -241,7 +241,7 @@
 			dr_mode = "host";
 		};
 
-		pcie@3400000 {
+		pcie1: pcie@3400000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03480000 0x0 0x40000   /* lut registers */
@@ -257,7 +257,7 @@
 				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie_ep@3400000 {
+		pcie_ep1: pcie_ep@3400000 {
 			compatible = "fsl,ls-pcie-ep";
 			reg = <0x00 0x03400000 0x0 0x80000
 			       0x00 0x034c0000 0x0 0x40000
@@ -268,7 +268,7 @@
 			big-endian;
 		};
 
-		pcie@3500000 {
+		pcie2: pcie@3500000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03580000 0x0 0x40000   /* lut registers */
@@ -285,7 +285,7 @@
 				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie_ep@3500000 {
+		pcie_ep2: pcie_ep@3500000 {
 			compatible = "fsl,ls-pcie-ep";
 			reg = <0x00 0x03500000 0x0 0x80000
 			       0x00 0x035c0000 0x0 0x40000
@@ -296,7 +296,7 @@
 			big-endian;
 		};
 
-		pcie@3600000 {
+		pcie3: pcie@3600000 {
 			compatible = "fsl,ls-pcie", "snps,dw-pcie";
 			reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 			       0x00 0x03680000 0x0 0x40000   /* lut registers */
@@ -312,7 +312,7 @@
 				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 		};
 
-		pcie_ep@3600000 {
+		pcie_ep3: pcie_ep@3600000 {
 			compatible = "fsl,ls-pcie-ep";
 			reg = <0x00 0x03600000 0x0 0x80000
 			       0x00 0x036c0000 0x0 0x40000

arch/arm/dts/fsl-ls1088a.dtsi

@@ -2,7 +2,7 @@
 /*
  * NXP ls1088a SOC common device tree source
  *
- * Copyright 2017 NXP
+ * Copyright 2017, 2020 NXP
  */
 
 / {
@@ -135,7 +135,7 @@
 		dr_mode = "host";
 	};
 
-	pcie@3400000 {
+	pcie1: pcie@3400000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03480000 0x0 0x80000   /* lut registers */
@@ -151,7 +151,7 @@
 			  0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie@3500000 {
+	pcie2: pcie@3500000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03580000 0x0 0x80000   /* lut registers */
@@ -167,7 +167,7 @@
 			  0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
 	};
 
-	pcie@3600000 {
+	pcie3: pcie@3600000 {
 		compatible = "fsl,ls-pcie", "snps,dw-pcie";
 		reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
 		       0x00 0x03680000 0x0 0x80000   /* lut registers */