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arch/arm/dts/imx6dl-aristainetos2b_7.dts deleted 100644 → 0
View file @ f36603c7
// SPDX-License-Identifier: (GPL-2.0)
/*
* support for the imx6 based aristainetos2 board
*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "imx6dl-aristainetos2_7.dtsi"
#include "imx6qdl-aristainetos2b.dtsi"
/ {
model = "aristainetos2b i.MX6 Dual Lite Board 7";
compatible = "fsl,imx6dl";
};
arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi deleted 100644 → 0
View file @ f36603c7
// SPDX-License-Identifier: GPL-2.0+ or X11
/*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
*/
#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi>
&lcd_panel {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp>;
enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
};
arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts deleted 100644 → 0
View file @ f36603c7
// SPDX-License-Identifier: (GPL-2.0)
/*
* support for the imx6 based aristainetos2b csl board
* parts for 4.3 inch LG display on spi1 port1
*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "imx6dl-aristainetos2_4.dtsi"
#include "imx6qdl-aristainetos2b_csl.dtsi"
/ {
model = "aristainetos2b csl i.MX6 Dual Lite Board 4";
compatible = "fsl,imx6dl";
};
&ecspi1 {
lcd_panel: display@0 {
compatible = "lg,lg4573";
spi-max-frequency = <10000000>;
reg = <1>;
power-on-delay = <10>;
display-timings {
480x800p57 {
native-mode;
clock-frequency = <27000027>;
hactive = <480>;
vactive = <800>;
hfront-porch = <10>;
hback-porch = <59>;
hsync-len = <10>;
vback-porch = <15>;
vfront-porch = <15>;
vsync-len = <15>;
hsync-active = <1>;
vsync-active = <1>;
};
};
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
};
arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts deleted 100644 → 0
View file @ f36603c7
// SPDX-License-Identifier: (GPL-2.0)
/*
* support for the imx6 based aristainetos2 board
*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "imx6dl-aristainetos2_7.dtsi"
#include "imx6qdl-aristainetos2b_csl.dtsi"
/ {
model = "aristainetos2b csl i.MX6 Dual Lite Board 7";
compatible = "fsl,imx6dl";
};
arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi deleted 100644 → 0
View file @ f36603c7
// SPDX-License-Identifier: GPL-2.0+ or X11
/*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
*/
#include <imx6qdl-aristainetos2c-u-boot.dtsi>
&lcd_panel {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ipu_disp>;
enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
backlight = <&backlight>;
};
arch/arm/dts/imx6dl-aristainetos2c_4.dts deleted 100644 → 0
View file @ f36603c7
// SPDX-License-Identifier: (GPL-2.0)
/*
* support for the imx6 based aristainetos2c board
* parts for 4.3 inch LG display on spi1 port1
*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
*
*/
/dts-v1/;
#include "imx6dl-aristainetos2_4.dtsi"
#include "imx6qdl-aristainetos2c.dtsi"
/ {
model = "aristainetos2c i.MX6 Dual Lite Board 4";
compatible = "fsl,imx6dl";
};
&ecspi1 {
lcd_panel: display@0 {
compatible = "lg,lg4573";
spi-max-frequency = <10000000>;
reg = <1>;
power-on-delay = <10>;
display-timings {
480x800p57 {
native-mode;
clock-frequency = <27000027>;
hactive = <480>;
vactive = <800>;
hfront-porch = <10>;
hback-porch = <59>;
hsync-len = <10>;
vback-porch = <15>;
vfront-porch = <15>;
vsync-len = <15>;
hsync-active = <1>;
vsync-active = <1>;
};
};
port {
panel_in: endpoint {
remote-endpoint = <&display_out>;
};
};
};
};
arch/arm/dts/imx6dl-aristainetos2c_7.dts
View file @ c4fddedc
...@@ -11,6 +11,6 @@ ...@@ -11,6 +11,6 @@
#include "imx6qdl-aristainetos2c.dtsi" #include "imx6qdl-aristainetos2c.dtsi"
/ { / {
model = "aristainetos2c i.MX6 Dual Lite Board 7"; model = "aristainetos2c+2d i.MX6 Dual Lite Boards 7";
compatible = "fsl,imx6dl"; compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl";
}; };
arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi → arch/arm/dts/imx6dl-aristainetos2c_cslb_7-u-boot.dtsi
View file @ c4fddedc
...@@ -3,7 +3,7 @@ ...@@ -3,7 +3,7 @@
* Copyright (C) 2019 Heiko Schocher <hs@denx.de> * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
*/ */
#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi> #include <imx6qdl-aristainetos2c_cslb-u-boot.dtsi>
/ { / {
vdd_panel_reg: regulator-panel { vdd_panel_reg: regulator-panel {
compatible = "regulator-fixed"; compatible = "regulator-fixed";
......
arch/arm/dts/imx6dl-aristainetos2_7.dts → arch/arm/dts/imx6dl-aristainetos2c_cslb_7.dts
View file @ c4fddedc
// SPDX-License-Identifier: (GPL-2.0) // SPDX-License-Identifier: (GPL-2.0)
/* /*
* support for the imx6 based aristainetos2 board * support for the imx6 based aristainetos2c cslb board
* *
* Copyright (C) 2019 Heiko Schocher <hs@denx.de> * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
* Copyright (C) 2015 Heiko Schocher <hs@denx.de> * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
...@@ -8,9 +8,9 @@ ...@@ -8,9 +8,9 @@
*/ */
/dts-v1/; /dts-v1/;
#include "imx6dl-aristainetos2_7.dtsi" #include "imx6dl-aristainetos2_7.dtsi"
#include "imx6qdl-aristainetos2.dtsi" #include "imx6qdl-aristainetos2c_cslb.dtsi"
/ { / {
model = "aristainetos2 i.MX6 Dual Lite Board 7"; model = "aristainetos2c cslb i.MX6 Dual Lite Board 7";
compatible = "fsl,imx6dl"; compatible = "abb,aristainetos2-imx6dl-7", "fsl,imx6dl";
}; };
arch/arm/dts/imx6q-ba16.dtsi
View file @ c4fddedc
...@@ -174,6 +174,17 @@ ...@@ -174,6 +174,17 @@
pinctrl-0 = <&pinctrl_enet>; pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
status = "okay"; status = "okay";
phy-handle = <&phy0>;
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: ethernet-phy@4 {
reg = <4>;
qca,clk-out-frequency = <125000000>;
};
};
}; };
&hdmi { &hdmi {
......
arch/arm/dts/imx6q-bx50v3-uboot.dtsi
View file @ c4fddedc
...@@ -27,7 +27,7 @@ ...@@ -27,7 +27,7 @@
#size-cells = <1>; #size-cells = <1>;
vpd@0 { vpd@0 {
reg = <0 1022>; reg = <0 800>;
}; };
bootcount: bootcount { bootcount: bootcount {
......
arch/arm/dts/imx6qdl-aristainetos2-common.dtsi
View file @ c4fddedc
// SPDX-License-Identifier: (GPL-2.0) // SPDX-License-Identifier: (GPL-2.0)
/* /*
* support for the imx6 based aristainetos2 board * support for the imx6 based aristainetos2 boards
* parts common to all versions * parts common to all versions
* *
* Copyright (C) 2019 Heiko Schocher <hs@denx.de> * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
...@@ -13,6 +13,8 @@ ...@@ -13,6 +13,8 @@
/ { / {
aliases { aliases {
eeprom0 = &i2c_eeprom0; eeprom0 = &i2c_eeprom0;
eeprom1 = &i2c_eeprom1;
eeprom2 = &i2c_eeprom2;
pmic0 = &i2c_pmic0; pmic0 = &i2c_pmic0;
}; };
...@@ -250,6 +252,12 @@ ...@@ -250,6 +252,12 @@
}; };
}; };
i2c_eeprom2: eeprom@57{
compatible = "atmel,24c64";
reg = <0x57>;
pagesize = <32>;
};
rtc@68 { rtc@68 {
compatible = "st,m41t11"; compatible = "st,m41t11";
reg = <0x68>; reg = <0x68>;
...@@ -274,6 +282,19 @@ ...@@ -274,6 +282,19 @@
}; };
}; };
&gpio2 {
tpm_pp {
gpio-hog;
output-low;
gpios = <17 GPIO_ACTIVE_HIGH>;
};
tpm_reset {
gpio-hog;
output-high;
gpios = <18 GPIO_ACTIVE_HIGH>;
};
};
&gpio6 { &gpio6 {
spi_bus_ena { spi_bus_ena {
gpio-hog; gpio-hog;
......
arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
View file @ c4fddedc
...@@ -50,28 +50,6 @@ ...@@ -50,28 +50,6 @@
}; };
}; };
&iomuxc {
pinctrl-0 = <&pinctrl_gpio &pinctrl_gpio_fix>;
u-boot,dm-pre-reloc;
pinctrl_gpio_fix: gpiofixgrp {
/*
* usdhc2 has a levelshifter on the carrier board Rev. DV1,
* that will automatically detect the driving direction.
* During initialisation this isn't working correctly,
* which causes DAT3 to be driven low towards the SD-card.
* This causes a SD-card enetring the SPI-Mode
* and therefore getting inaccessible until next power cycle.
* As workaround we drive the DAT3 line as GPIO and set it high.
* This makes usdhc2 unusable in u-boot, but works for the
* initialisation in Linux
*/
fsl,pins = <
MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x20000
>;
};
};
&gpio1 { &gpio1 {
usdhc_fix { usdhc_fix {
gpio-hog; gpio-hog;
......
arch/arm/dts/imx6qdl-aristainetos2.dtsi deleted 100644 → 0
View file @ f36603c7
// SPDX-License-Identifier: (GPL-2.0)
/*
* support for the imx6 based aristainetos2 board
*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
*
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
#include "imx6qdl-aristainetos2-common.dtsi"
/ {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio>;
LED_blue {
label = "led_blue";
gpios = <&gpio2 29 GPIO_ACTIVE_LOW>;
};
LED_green {
label = "led_green";
gpios = <&gpio5 4 GPIO_ACTIVE_LOW>;
};
LED_red {
label = "led_red";
gpios = <&gpio2 28 GPIO_ACTIVE_LOW>;
};
LED_yellow {
label = "led_yellow";
gpios = <&gpio6 16 GPIO_ACTIVE_LOW>;
};
LED_ena {
label = "led_ena";
gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
};
};
};
&ecspi1 {
fsl,spi-num-chipselects = <3>;
cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH
&gpio4 10 GPIO_ACTIVE_HIGH
&gpio4 11 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
};
&ecspi4 {
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
status = "okay";
pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
flash: m25p80@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a11", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <1>;
};
};
&gpio7 {
sd2_driver_ena {
gpio-hog;
output-high;
gpios = <8 GPIO_ACTIVE_HIGH>;
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
no-1-8-v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
no-1-8-v;
status = "okay";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */
>;
};
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 /* WP pin */
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
/* led enable */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0
/* LCD power enable */
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0
/* led yellow */
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0
/* led red */
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0
/* led green */
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0
/* led blue */
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0
/* Profibus IRQ */
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
/* FPGA IRQ currently unused*/
MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
/* Display reset because of clock failure */
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0
/* spi bus #2 SS driver enable */
MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
/* RST_LOC# PHY reset input (has pull-down!)*/
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0
/* USB_OTG_ID = GPIO1_24*/
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x4001b0b0
/* Touchscreen IRQ */
MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
/* PCIe reset */
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
>;
};
pinctrl_gpmi_nand: gpmi-nand {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
/* SD1 card detect input */
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
/* SD1 write protect input */
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
/* SD2 level shifter output enable */
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
/* SD2 card detect input */
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
/* SD2 write protect input */
MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
>;
};
};
arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi deleted 100644 → 0
View file @ f36603c7
// SPDX-License-Identifier: GPL-2.0+ or X11
/*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
*/
/ {
chosen {
u-boot,dm-pre-reloc;
stdout-path = &uart2;
};
wdt-reboot {
compatible = "wdt-reboot";
wdt = <&wdog1>;
};
};
&uart2 {
u-boot,dm-pre-reloc;
};
&pinctrl_gpio {
u-boot,dm-pre-reloc;
};
&pinctrl_uart2 {
u-boot,dm-pre-reloc;
};
&iomuxc {
u-boot,dm-pre-reloc;
};
&aips2 {
u-boot,dm-pre-reloc;
};
&backlight {
pwms = <&pwm1 0 300000>;
default-brightness-level = <2>;
};
/*
* allow switching write protect / reset pin by gpio,
* because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot
*/
&gpio2 {
u-boot,dm-pre-reloc;
wp_spi_nor {
gpio-hog;
output-high;
gpios = <15 GPIO_ACTIVE_HIGH>;
};
reset_spi_nor {
gpio-hog;
output-high;
gpios = <28 GPIO_ACTIVE_HIGH>;
};
};
&gpio4 {
u-boot,dm-pre-reloc;
};
&ecspi1 {
u-boot,dm-pre-reloc;
};
&flash {
u-boot,dm-pre-reloc;
};
&pinctrl_ecspi1 {
u-boot,dm-pre-reloc;
};
arch/arm/dts/imx6qdl-aristainetos2b.dtsi deleted 100644 → 0
View file @ f36603c7
// SPDX-License-Identifier: (GPL-2.0)
/*
* support for the imx6 based aristainetos2b board
*
* Copyright (C) 2019 Heiko Schocher <hs@denx.de>
* Copyright (C) 2015 Heiko Schocher <hs@denx.de>
*
*/
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/imx6qdl-clock.h>
#include "imx6qdl-aristainetos2-common.dtsi"
/ {
leds {
compatible = "gpio-leds";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio>;
LED_blue {
label = "led_blue";
gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>;
};
LED_green {
label = "led_green";
gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
};
LED_red {
label = "led_red";
gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>;
};
LED_yellow {
label = "led_yellow";
gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>;
};
LED_ena {
label = "led_ena";
gpios = <&gpio1 25 GPIO_ACTIVE_LOW>;
};
};
};
&ecspi1 {
fsl,spi-num-chipselects = <3>;
cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH
&gpio4 10 GPIO_ACTIVE_HIGH
&gpio4 11 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi1>;
status = "okay";
pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;
pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
flash: m25p80@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,n25q128a11", "jedec,spi-nor";
spi-max-frequency = <20000000>;
reg = <0>;
};
};
&ecspi4 {
fsl,spi-num-chipselects = <2>;
cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi4>;
status = "okay";
};
&i2c1 {
tpm@20 {
compatible = "infineon,slb9645tt";
reg = <0x20>;
};
};
&gpio7 {
sd2_driver_ena {
gpio-hog;
output-high;
gpios = <8 GPIO_ACTIVE_HIGH>;
};
};
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
status = "okay";
};
&can2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>;
cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>;
no-1-8-v;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
/*
* comment out this line to make the WiFi Eval-Module work in
* SD-Slot2, and add line:
* broken-cd;
* causes 6% CPU load if no WiFi module installed (polling)
*/
cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
no-1-8-v;
status = "okay";
};
&iomuxc {
pinctrl_ecspi1: ecspi1grp {
fsl,pins = <
MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
/* SS0# */
MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1
/* SS1# */
MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1
/* SS2# */
MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1
/* WP pin NOR Flash */
MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0
/* Flash nReset */
MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0
>;
};
pinctrl_ecspi4: ecspi4grp {
fsl,pins = <
MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1
MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1
MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1
MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */
MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */
>;
};
pinctrl_gpio: gpiogrp {
fsl,pins = <
/* led enable */
MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0
/* LCD power enable */
MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0
/* led yellow */
MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0
/* led red */
MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0
/* led green */
MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0
/* led blue */
MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0
/* Profibus IRQ */
MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0
/* FPGA IRQ currently unused*/
MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0
/* Display reset because of clock failure */
MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0
/* spi bus #2 SS driver enable */
MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0
/* RST_LOC# PHY reset input (has pull-down!)*/
MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0
/* Touchscreen IRQ */
MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0
/* PCIe reset */
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
/* make sure pin is GPIO and not ENET_REF_CLK */
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0
/* SD2 level shifter output enable / SD2 Reset# */
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
>;
};
pinctrl_gpmi_nand: gpmi-nand {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_flexcan1: flexcan1grp {
fsl,pins = <
MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0
MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0
>;
};
pinctrl_flexcan2: flexcan2grp {
fsl,pins = <
MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0
MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0
>;
};
pinctrl_usbotg: usbotggrp {
fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
/* SD1 card detect input */
MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0
/* SD1 write protect input */
MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71
/* SD2 card detect input */
MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
/* SD2 write protect input */
MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0
>;
};
};
arch/arm/dts/imx6qdl-aristainetos2c.dtsi
View file @ c4fddedc
// SPDX-License-Identifier: (GPL-2.0) // SPDX-License-Identifier: (GPL-2.0)
/* /*
* support for the imx6 based aristainetos2c board * support for the imx6 based aristainetos2c+2d boards
* *
* Copyright (C) 2019 Heiko Schocher <hs@denx.de> * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
* Copyright (C) 2015 Heiko Schocher <hs@denx.de> * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
...@@ -79,6 +79,14 @@ ...@@ -79,6 +79,14 @@
}; };
}; };
&gpio7 {
eMMC_reset {
gpio-hog;
output-high;
gpios = <8 GPIO_ACTIVE_HIGH>;
};
};
&can1 { &can1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>; pinctrl-0 = <&pinctrl_flexcan1>;
...@@ -172,6 +180,8 @@ ...@@ -172,6 +180,8 @@
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0 MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0
/* TPM Reset */ /* TPM Reset */
MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0
/* eMMC Reset# */
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
>; >;
}; };
......
arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi → arch/arm/dts/imx6qdl-aristainetos2c_cslb.dtsi
View file @ c4fddedc
// SPDX-License-Identifier: (GPL-2.0) // SPDX-License-Identifier: (GPL-2.0)
/* /*
* support for the imx6 based aristainetos2b-csl board * support for the imx6 based aristainetos2c-cslb board
* *
* Copyright (C) 2019 Heiko Schocher <hs@denx.de> * Copyright (C) 2019 Heiko Schocher <hs@denx.de>
* Copyright (C) 2015 Heiko Schocher <hs@denx.de> * Copyright (C) 2015 Heiko Schocher <hs@denx.de>
...@@ -104,19 +104,13 @@ ...@@ -104,19 +104,13 @@
}; };
&gpio7 { &gpio7 {
wlan_reset { eMMC_reset {
gpio-hog; gpio-hog;
output-high; output-high;
gpios = <8 GPIO_ACTIVE_HIGH>; gpios = <8 GPIO_ACTIVE_HIGH>;
}; };
}; };
&gpmi {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>;
status = "okay";
};
&usdhc1 { &usdhc1 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-0 = <&pinctrl_usdhc1>;
...@@ -127,7 +121,9 @@ ...@@ -127,7 +121,9 @@
&usdhc2 { &usdhc2 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <8>;
no-1-8-v; no-1-8-v;
non-removable;
status = "okay"; status = "okay";
}; };
...@@ -190,31 +186,15 @@ ...@@ -190,31 +186,15 @@
MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0
/* make sure pin is GPIO and not ENET_REF_CLK */ /* make sure pin is GPIO and not ENET_REF_CLK */
MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0
/* WLAN Module Reset# */ /* TPM PP */
MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0
/* TPM Reset */
MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0
/* eMMC Reset# */
MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0
>; >;
}; };
pinctrl_gpmi_nand: gpmi-nand {
fsl,pins = <
MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
>;
};
pinctrl_usbotg: usbotggrp { pinctrl_usbotg: usbotggrp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
...@@ -237,12 +217,16 @@ ...@@ -237,12 +217,16 @@
pinctrl_usdhc2: usdhc2grp { pinctrl_usdhc2: usdhc2grp {
fsl,pins = < fsl,pins = <
MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
>; >;
}; };
}; };
arch/arm/dts/imx6ull-dart-6ul.dtsi
View file @ c4fddedc
...@@ -14,6 +14,10 @@ ...@@ -14,6 +14,10 @@
chosen { chosen {
stdout-path = &uart1; stdout-path = &uart1;
}; };
aliases {
eeprom0 = &eeprom_som;
};
}; };
&fec1 { &fec1 {
...@@ -52,6 +56,10 @@ ...@@ -52,6 +56,10 @@
}; };
}; };
&gpio1 {
u-boot,dm-pre-reloc;
};
&gpmi { &gpmi {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpmi_nand>; pinctrl-0 = <&pinctrl_gpmi_nand>;
...@@ -96,10 +104,13 @@ ...@@ -96,10 +104,13 @@
scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
u-boot,dm-pre-reloc;
eeprom@50 { eeprom_som: eeprom@50 {
compatible = "cat,24c32"; u-boot,dm-pre-reloc;
compatible = "atmel,24c04";
reg = <0x50>; reg = <0x50>;
status = "okay";
}; };
}; };
...@@ -205,6 +216,7 @@ ...@@ -205,6 +216,7 @@
}; };
pinctrl_i2c2: i2cgrp { pinctrl_i2c2: i2cgrp {
u-boot,dm-pre-reloc;
fsl,pins = < fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
...@@ -212,6 +224,7 @@ ...@@ -212,6 +224,7 @@
}; };
pinctrl_i2c2_gpio: i2c2grp_gpio { pinctrl_i2c2_gpio: i2c2grp_gpio {
u-boot,dm-pre-reloc;
fsl,pins = < fsl,pins = <
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0 MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0 MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
......